参数资料
| 型号： | ZY7015LG-T1 |
| 厂商： | Power-One |
| 文件页数： | 26/34页 |
| 文件大小： | 0K |
| 描述： | PROGBL CONV DC-DC 15A OUT SMD |
| 标准包装： | 500 |
| 系列： | 智能 POL 转换器 |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 3V |
| 电压 - 输入（最大）： | 13.2V |
| Voltage - Output 1： | 0.5 ~ 5.5 V |
| 电流 - 输出（最大）： | 15A |
| 电源（瓦） - 制造商系列： | 82W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 模块 |
| 尺寸/尺寸： | 1.26" L x 0.55" W x 0.31" H（32.0mm x 14.0mm x 8.0mm） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
| 电源（瓦特）- 最大： | 82.5W |
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ZY7015 15A DC-DC Intelligent POL Data Sheet
3V to 13.2V Input ? 0.5V to 5.5V Output
8.4
PWM Parameters
R/W-0
R/W-0
R/W-0
R/W-0 1)
R/W-0 1)
R/W-0 1)
R/W-0 1)
R/W-0 1)
Z-Series POLs utilize the digital PWM controller.
FRQ2
FRQ1
FRQ0
INT4
INT3
INT2
INT1
INT0
The controller enables users to program most of the
PWM performance parameters, such as switching
frequency, interleave, duty cycle, and feedback loop
compensation.
Bit 7
Bit 7:5 FRQ[2:0] : PWM Frequency Selection
000: 500kHz
001: 750kHz
010: 1000lHz
011: 1250kHz
100: 1250kHz
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Initial value depends on the state of the Interleave Mode ( IM ) Input:
8.4.1 Switching Frequency
The switching frequency can be programmed in the
GUI PWM Controller window shown in Figure 47 or
directly via the I 2 C bus by writing into the INT register
shown in Figure 48. Note that the content of the
register can be changed only when the POL is
turned off.
101: 1500kHz
110: 1750kHz
111: 2000kHz
Bit 4:0 INT[4:0] : Interleave position
00h: Ton starts with 0.0° Phase lag to SD Line
01h: Ton starts wi th 11.25° Phase lag to SD Line
02h: Ton starts with 22.50° Phase lag to SD Line
…
1Fh: Ton starts with 348.75° Phase lag to SD Line
1)
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded
Switching actions of all POLs connected to the SD
IM=Low:
At POR reset a 0 is loaded
line are synchronized to the master clock generated
by the DPM. Each POL is equipped with a PLL and
a frequency divider so they can operate at multiples
(including fractional) of the master clock frequency
as programmed by a user. The POL converters can
operate at 500 kHz, 750 kHz, and 1 MHz. Although
synchronized, switching frequencies of different
POLs are independent of each other. It is
permissible to mix POLs operating at different
frequencies in one system. It allows optimizing
efficiency and transient response of each POL in the
system individually.
Figure 48. Interleave Configuration Register INT
8.4.2 Interleave
Interleave is defined as a phase delay between the
synchronizing slope of the master clock on the SD
pin and PWM signal of a POL. The interleave can
be programmed in the GUI PWM Controller window
or directly via the I 2 C bus by writing into the INT
register.
Every POL generates switching noise. If no
interleave is programmed, all POLs in the system
switch simultaneously and noise reflected to the
input source from all POLs is added together as
shown in Figure 49.
Figure 49. Input Voltage Noise, No Interleave
Figure 47. PWM Controller Window
ZD-00283 Rev. 2.5, 01-Jul-10
www.power-one.com
Page 26 of 34
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZY7015LGT2 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:3V to 13.2V Input 0.5V to 5.5V Output |
| ZY7015LG-T2 | 功能描述:DC/DC转换器 15A OUT SMD 100 pcs RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ZY7015LGT3 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:3V to 13.2V Input 0.5V to 5.5V Output |
| ZY7015LG-T3 | 功能描述:DC/DC转换器 50 pcs RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ZY7015LQ1 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:3V to 13.2V Input 0.5V to 5.5V Output |
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