- 您现在的位置：买卖IC网 > Datasheet目录892 > ZY8110G (Power-One)PROGBL CONVERT DC-DC 10A OUT THR Datasheet资料下载
参数资料
| 型号： | ZY8110G |
| 厂商： | Power-One |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | PROGBL CONVERT DC-DC 10A OUT THR |
| 特色产品： | ZY Series Converters |
| 标准包装： | 48 |
| 系列： | 智能 POL 转换器 |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 8V |
| 电压 - 输入（最大）： | 14V |
| Voltage - Output 1： | 0.5 ~ 5.5 V |
| 电流 - 输出（最大）： | 10A |
| 电源（瓦） - 制造商系列： | 55W |
| 安装类型： | 通孔 |
| 封装/外壳： | 11-SIP 模块 |
| 尺寸/尺寸： | 1.20" L x 0.26" W x 0.84" H（30.5mm x 6.7mm x 21.4mm） |
| 包装： | 托盘 |
| 工作温度： | 0°C ~ 70°C |
| 效率： | 91.6% |
| 电源（瓦特）- 最大： | 55W |
| 产品目录页面： | 2739 (CN2011-ZH PDF) |
| 其它名称： | 179-2403 ZY8110G-R1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页
ZY8110 10A DC-DC Intelligent POL
8V to 14V Input ? 0.5V to 5.5V Output
Data Sheet
Figure 41 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 67.5°, 180°, and 303.75°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction. To
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the GUI PWM
Controller window or directly via the I 2 C bus by
writing into the DCL register shown in Figure 42.
achieve similar noise reduction without the interleave
will require the addition of an external LC filter.
R/W-1
DCL5
R/W-1
DCL4
R/W-1
DCL3
R/W -0
DCL2
R/W -1
DCL1
R/W-0
DCL0
R/W-0
HI
R/W-0
LO
Bit 7
Bit 7:2 DCL[5:0] , Duty Cycle Limitation
00h: 0
01h: 1/192
…
3Fh: 63/192
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 1:
Bit 0:
HI , ADC high saturation feed -forward
0: disabled
1: enabled
LO , ADC low saturation feed -forward
0: disabled
1: enabled
Figure 42. Duty Cycle Limit Register
8.4.4 ADC Saturation Feedforward
To speed up the PWM response in case of heavy
dynamic loads, the duty cycle can be forced either to
DC ?
,
Figure 41. Input Voltage Noise with Interleave
ZY8110 interleave is independent of the number of
POLs in a system and is fully programmable in
11.25 ? steps. It allows maximum output noise
reduction by intelligently spreading switching energy.
Note : Due to noise sensitivity issues that may occur in limited
cases, it is recommended to avoid phase lag settings of
112.5 and 123.75 degrees, otherwise false PG and/or OV
indications may occur.
8.4.3 Duty Cycle Limit
The ZY8110 is a step-down converter therefore V OUT
is always less than V IN . The relationship between
the two parameters is characterized by the duty
cycle and can be estimated from the following
equation:
V OUT
V IN . MIN
Where, DC is the duty cycle, V OUT is the required
maximum output voltage (including margining),
V IN.MIN is the minimum input voltage.
It is good practice to limit the maximum duty cycle of
the PWM controller to a somewhat higher value
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
two comparators defining a window around the
output voltage setpoint. When an error signal is
inside the window, it will produce gradual duty cycle
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
output current steps), the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
controller, reducing amount of required external
capacitance.
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
overcompensation of the output error. The
phenomenon manifests itself as low frequency
oscillations on the output of the POL. It can usually
be reduced or eliminated by disabling the ADC
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V.
The ADC saturation feedforward can be
programmed in the GUI PWM Controller window or
ZD-01991 Rev. 1.1, 01-Jul-10
www.power-one.com
Page 23 of 28
相关PDF资料 |
PDF描述 |
|---|---|
| ZY8140G | PROGBL CONVERT DC-DC 40A OUT THU |
| ZY8160G | PROGBL CONVERT DC-DC 60A OUT THU |
| 0006660012 | CABLE 28AWG 148MM RED |
| 0006660013 | CABLE 28AWG 300MM RED |
| 002679-000 | CABLE 22AWG TWISTED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZY8110G-R1 | 功能描述:DC/DC转换器 8-14Vin 10A(max) 0.5-5.5Vout 31mA RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ZY8120G-R1 | 功能描述:DC/DC转换器 8-14Vin 5V OUT 20A INTELLIGENT POL CONV RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ZY8140(G)-ln | 功能描述:DC/DC转换器 "ln" - packout option RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ZY8140G | 功能描述:PROGBL CONVERT DC-DC 40A OUT THU RoHS:是 类别:电源 - 板载 >> DC DC Converters 系列:智能 POL 转换器 标准包装:15 系列:Econoline REC5 类型:隔离 输出数:2 电压 - 输入（最小）:18V 电压 - 输入（最大）:72V Voltage - Output 1:15V Voltage - Output 2:-15V Voltage - Output 3:- 电流 - 输出（最大）:170mA，170mA 电源（瓦） - 制造商系列:5W 电压 - 隔离:2kV（2000V） 特点:- 安装类型:表面贴装 封装/外壳:24-DIP SMD 模块（18 引线） 尺寸/尺寸:1.26" L x 0.78" W x 0.44" H（32.0mm x 19.9mm x 11.2mm） 包装:管件 工作温度:-40°C ~ 75°C 效率:85% 电源（瓦特）- 最大:5W 其它名称:10010755 |
| ZY8140G-B2 | 制造商:Power-One 功能描述: |
发布紧急采购，3分钟左右您将得到回复。