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| 型号： | 1893YI-10 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, INTERFACE CIRCUIT, PQFP64 |
| 封装： | 10 X 10 MM, TQFP-64 |
| 文件页数： | 18/152页 |
| 文件大小： | 943K |
| 代理商： | 1893YI-10 |
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ICS1893 Rev C 6/6/00
June, 2000
114
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
RXD0,
RXD1,
RXD2,
RXD3
35,
34,
33,
32
Output
Receive Data 0–3.
RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
While the ICS1893 asserts RXDV, the ICS1893 transfers the receive
data signals on the RXD0–RXD3 pins to the MAC/Repeater Interface
synchronously on the rising edges of RXCLK.
RXDV
36
Output
Receive Data Valid.
The ICS1893 asserts RXDV to indicate to the MAC/repeater that data is
available on the MII Receive Bus (RXD[3:0]). The ICS1893:
Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see Chapter 10.5.6, “MII /
100M Stream Interface: Synchronous Receive Timing”.)
De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
RXER
39
Output
Receive Error.
When the MAC/Repeater Interface is in:
10M MII mode, RXER is not used.
100M MII mode, the ICS1893 asserts a signal on the RXER pin when
either of the following two conditions are true:
– Errors are detected during the reception of valid frames
– A False Carrier is detected
Note:
1. An ICS1893 asserts a signal on the RXER pin upon detection of a
False Carrier so that repeater applications can prevent the
propagation of a False Carrier.
2. The RXER signal always transitions synchronously with RXCLK.
3. The signal on RXER pin is conditioned by the RXTRI pin.
RXTRI
41
Input
Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin is logic:
Low, the MAC indicates that it is not in a tri-state condition.
High, the MAC indicates that it is in a tri-state condition. In this case,
the ICS1893 acts to ensure that only one PHY is active at a time.
TXCLK
43
Output
Transmit Clock.
The ICS1893 generates this clock signal to synchronize the transfer of
data from the MAC/Repeater Interface to the ICS1893. When the mode is:
10Base-T, the TXCLK frequency is 2.5 MHz.
100Base-TX, the TXCLK frequency is 25 MHz.
TXD0,
TXD1,
TXD2,
TXD3
45,
46,
47,
48
Input
Transmit Data 0–3.
TXD0 is the least-significant bit and TXD3 is the most-significant bit of
the MII transmit data nibble received from the MAC/repeater.
The ICS1893 samples its TXEN signal to determine when data is
available for transmission. When TXEN is asserted, the signals on a
the TXD[3:0] pins are sampled synchronously on the rising edges of
the TXCLK signal.
Table 9-5.
MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
Pin
Number
Pin
Type
Pin Description
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相关代理商/技术参数 |
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| 1893YI-10LF | 功能描述:以太网 IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| 1893YI-10LFT | 功能描述:以太网 IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| 1894 | 功能描述:支架与垫片 HEX .187X.625 ALUM RoHS:否 制造商:Schurter 类型:Transipillar Spacers 长度:16 m 螺纹大小:M4 外径:10 mm 材料:Nylon with Steel 电镀:Zinc |
| 1894# | 制造商:Fluke Electronics 功能描述:BNC (F)/BANANA PLUG 制造商:Pomona Electronics 功能描述: |
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