参数资料
| 型号： | 24AA1025-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1MBIT 400KHZ 8SOIC |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1M (128K x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
24AA1025/24LC1025/24FC1025
AC CHARACTERISTICS (Continued)
Industrial (I): V CC = +1.7V to 5.5V T A = -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T A = -40°C to +125°C
Param.
No.
11
Sym.
T SU : WP
Characteristic
WP setup time
Min.
4000
Max.
—
Units
ns
Conditions
1.7V ? V CC ? 2.5V
4000
600
600
600
—
—
—
—
2.5V ? V CC ? 4.5V, E-temp
2.5V ? V CC ? 5.5V
1.8V ? V CC ? 2.5V (24FC1025 only)
2.5V ? V CC ? 5.5V (24FC1025 only)
12
T HD : WP
WP hold time
4700
—
ns
1.7V ? V CC ? 2.5V
4700
1300
1300
1300
—
—
—
—
2.5V ? V CC ? 4.5V, E-temp
2.5V ? V CC ? 5.5V
1.8V ? V CC ? 2.5V (24FC1025 only)
2.5V ? V CC ? 5.5V (24FC1025 only)
13
T AA
Output valid from clock
—
3500
ns
1.7V ? V CC ? 2.5V
( Note 2 )
—
—
—
—
3500
900
900
400
2.5V ? V CC ? 4.5V, E-temp
2.5V ? V CC ? 5.5V
1.8V ? V CC ? 2.5V (24FC1025 only)
2.5V ? V CC ? 5.5V (24FC1025 only)
14
T BUF
Bus free time: Time the bus
4700
—
ns
1.7V ? V CC ? 2.5V
must be free before a new
transmission can start
4700
1300
1300
500
—
—
—
—
2.5V ? V CC ? 4.5V, E-temp
2.5V ? V CC ? 5.5V
1.8V ? V CC ? 2.5V (24FC1025 only)
2.5V ? V CC ? 5.5V (24FC1025 only)
15
T SP
Input filter spike suppression
—
50
ns
All except 24FC1025 ( Note 1 and Note 3 )
(SDA and SCL pins)
16
T WC
Write cycle time (byte or page)
—
5
ms
—
17
Endurance
1,000,000
—
cycles Page mode, 25°C, V CC = 5.5V ( Note 4 )
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance? Model which can be obtained from Microchip’s web site at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
IN
7
6
3
8
9
10
15
SDA
OUT
13
14
WP
(protected)
(unprotected)
11
12
DS21941K-page 4
? 2005-2012 Microchip Technology Inc.
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