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参数资料
| 型号： | 24AA64FT-I/MNY |
| 厂商： | Microchip Technology |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC SRL EEPROM 8KX8 1.8V 8-TDFN |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.71 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN（2x3） |
| 包装： | 标准包装 |
| 产品目录页面： | 1446 (CN2011-ZH PDF) |
| 其它名称： | 24AA64FT-I/MNYDKR |
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24AA64F/24LC64F/24FC64F
4.0
BUS CHARACTERISTICS
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition
Accordingly, the following bus conditions have been
defined ( Figure 4-1 ).
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty two will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.1
Bus Not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
4.2
Start Data Transfer (B)
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Note:
The 24XX64F does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
4.3
Stop Data Transfer (C)
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
4.4
Data Valid (D)
data to the slave by not generating an Acknowledge bit
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64F) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Data
Allowed
Stop
Condition
DS22154B-page 6
Valid
to Change
? 2009-2012 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24AA64-I/MNY | 功能描述:电可擦除可编程只读存储器 64K 8K X 8 1.8V SER EE IND RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24AA64-I/MNY-P9038V254MM | 功能描述:- EEPROM Kit 制造商:idt, integrated device technology inc 系列:- 零件状态:有效 配件类型:EEPROM 套件 配套使用产品/相关产品:- 标准包装:1 |
| 24AA64-I/MS | 功能描述:电可擦除可编程只读存储器 8kx8 - 1.8V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24AA64-I/MSG | 功能描述:电可擦除可编程只读存储器 8kx8 - 1.8V Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24AA64-I/P | 功能描述:电可擦除可编程只读存储器 8kx8 - 1.8V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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