参数资料
| 型号： | 24C00T/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 128BIT 400KHZ 8TSSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128（16 x 8） |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
24AA00/24LC00/24C00
2.0
PIN DESCRIPTIONS
4.0
BUS CHARACTERISTICS
2.1
SDA Serial Data
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V CC (typical 10 k Ω for 100 kHz, 2 k Ω for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
2.2
SCL Serial Clock
4.1
Bus Not Busy (A)
This input is used to synchronize the data transfer from
Both data and clock lines remain high.
and to the device.
4.2
Start Data Transfer (B)
2.3
Noise Protection
A high-to-low transition of the SDA line while the clock
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
proper device operation even on a noisy bus.
4.3
Stop Data Transfer (C)
3.0
FUNCTIONAL DESCRIPTION
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
operations must be ended with a Stop condition.
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
4.4
Data Valid (D)
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
DS21178G-page 4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
? 2007 Microchip Technology Inc.
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