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参数资料
| 型号： | 24FC1026T-I/SM |
| 厂商： | Microchip Technology |
| 文件页数： | 12/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1024KB 1MHZ 8-SOIJ |
| 标准包装： | 2,100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1M (128K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIJ |
| 包装： | 带卷 (TR) |
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24AA1026/24LC1026/24FC1026
8.0
READ OPERATION
8.2
Random Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX1026 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX1026 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX1026 as part of a write operation (R/W bit set to
0 ). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again, but with the R/W bit set to a one.
The 24XX1026 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX1026 to discontinue
transmission ( Figure 8-2 ). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
the transfer, but does generate a Stop condition and the
24XX1026 discontinues transmission ( Figure 8-1 ).
8.3
Sequential Read
FIGURE 8-1:
CURRENT ADDRESS
READ
Sequential reads are initiated in the same way as a
random read except that after the 24XX1026 transmits
the first data byte, the master issues an acknowledge
BUS ACTIVITY
MASTER
S
T
A
R
T
Control
Byte
Data
Byte
S
T
O
P
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX1026 to
transmit the next sequentially addressed 8-bit word
( Figure 8-3 ). Following the final byte transmitted to the
S 1 0 1 0 A AB 1
SDA LINE
BUS ACTIVITY
2 1 0
A
C
K
N
O
A
C
K
P
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX1026 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows half the memory contents to be serially read
during one operation. Sequential read address
boundaries are 00000h to 0FFFFh and 10000h to
1FFFFh. The internal Address Pointer will
automatically roll over from address 0FFFFh to
address 00000h if the master acknowledges the byte
received from the array address, 0FFFFh. The internal
address counter will automatically roll over from
address 1FFFFh to address 10000h if the master
acknowledges the byte received from the array
address, 1FFFFh.
DS22270C-page 12
? 2011-2012 Microchip Technology Inc.
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