参数资料
| 型号： | 25A512T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KBIT 10MHZ 8SOIC |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.7 V ~ 3 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
25A512
2.8
PAGE ERASE
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable ( WREN ) instruc-
tion must be given prior to attempting a PAGE ERASE .
This is done by setting CS low and then clocking out
the proper instruction into the 25A512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
FIGURE 2-8:
CS
PAGE ERASE SEQUENCE
0
1
2
3
4
5
6
7
8
9 1 0 11
2 1 2 2 2 3
SCK
Instruction
16-bit Address
SI
1
1
0
1
1
0
0
0 15 14 13 12
2
1
0
High-Impedance
SO
? 2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 15
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 25A512TIST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:512 Kbit SPI Bus Serial EEPROM |
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| 25-A659-00-00NP | 制造商:Sumida Corporation 功能描述:- Bulk |
| 25A699A | 制造商:PANA 功能描述: |
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