参数资料
| 型号： | 25A512T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 17/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KBIT 10MHZ 8SOIC |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.7 V ~ 3 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
25A512
2.10
CHIP ERASE
The CHIP ERASE instruction will erase all bits (FFh) in
the array. A Write Enable ( WREN ) instruction must be
given prior to executing a CHIP ERASE . This is done
by setting CS low and then clocking out the proper
instruction into the 25A512. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The CHIP ERASE instruction is entered by driving the
CS low, followed by the instruction code (Figure 2-10)
onto the SI line.
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the CHIP
ERASE instruction will not be executed. Once the CS
pin is driven high the self-timed CHIP ERASE instruc-
tion begins. While the device is executing the CHIP
ERASE instruction the WIP bit in the STATUS register
can be read to determine when the CHIP ERASE
instruction is complete.
The CHIP ERASE instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ?,
?, or all of the array is protected.
FIGURE 2-10:
CHIP ERASE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
1
1
0
0
0
1
1
1
High-Impedance
SO
? 2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 17
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相关代理商/技术参数 |
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|---|---|
| 25A512TIST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:512 Kbit SPI Bus Serial EEPROM |
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| 25-A659-00-00NP | 制造商:Sumida Corporation 功能描述:- Bulk |
| 25A699A | 制造商:PANA 功能描述: |
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