参数资料
| 型号： | 25A512T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 20/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KBIT 10MHZ 8SOIC |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.7 V ~ 3 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
25A512
3.0
PIN DESCRIPTIONS
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
The descriptions of the pins are listed in Table 3-1.
install the 25A512 in a system with WP pin grounded
and still be able to write to the STATUS register. The
TABLE 3-1:
PIN FUNCTION TABLE
WP pin functions will be enabled when the WPEN bit is
Name
Pin Number
Function
set high.
CS
1
Chip Select Input
3.4
Serial Input (SI)
SO
WP
V SS
2
3
4
Serial Data Output
Write-Protect Pin
Ground
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
SI
5
Serial Data Input
3.5
Serial Clock (SCK)
SCK
HOLD
V CC
6
7
8
Serial Clock Input
Hold Input
Supply Voltage
The SCK is used to synchronize the communication
between a master and the 25A512. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.1
Chip Select (CS)
A low level on this pin selects the device. A high level
3.6
Hold (HOLD)
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
The HOLD pin is used to suspend transmission to the
25A512 while in the middle of a serial sequence without
having to re-transmit the entire sequence over again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence.
The HOLD pin shoul d be brought low while SCK is low,
otherwise the HOLD function will not be invoked until
the next SCK high-to-low transition. The 25A512 must
remain selected during this sequence. The SI and SCK
3.2
Serial Output (SO)
levels are “don’t cares” during the time the device is
paused and any transitions on these pins w ill be
The SO pin is used to transfer data out of the 25A512.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
ignored. To resume serial communication, HOLD
should be brought high while the SCK pin is low, other-
wise serial communication will not be resumed until the
next SCK high-to-low transition.
3.3
Write-Protect (WP)
The SO line will tri-state immediately upon a high-to-
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
low transition of the HOLD pin, and will begin outputting
again immediately upon a subsequent low-to-high
transition of the HOLD pin, independent of the state of
SCK.
DS22237C-page 20
Preliminary
? 2010-2011 Microchip Technology Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| 24LC65T/SM | IC EEPROM 64KBIT 400KHZ 8SOIC |
| XC6SLX150-2FGG900I | IC FPGA SPARTAN 6 147K 900FGGBGA |
| 24LC65T-I/SM | IC EEPROM 64KBIT 400KHZ 8SOIC |
| SST39VF200A-70-4C-B3KE | IC FLASH MPF 2MBIT 70NS 48TFBGA |
| 24FC512T-I/ST | IC EEPROM 512KBIT 1MHZ 8TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 25A512TIST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:512 Kbit SPI Bus Serial EEPROM |
| 25A6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PENTODE POWER AMPLIFIER |
| 25-A659-00-00NP | 制造商:Sumida Corporation 功能描述:- Bulk |
| 25A699A | 制造商:PANA 功能描述: |
| 25A6GT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PENTODE POWER AMPLIFIER |
发布紧急采购，3分钟左右您将得到回复。