参数资料
| 型号： | 25LC256-I/MF |
| 厂商： | Microchip Technology |
| 文件页数： | 13/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256KBIT 10MHZ 8DFN |
| 标准包装： | 60 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN-S（6x5） |
| 包装： | 管件 |
| 产品目录页面： | 1450 (CN2011-ZH PDF) |
25AA256/25LC256
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX256 in a system with WP pin grounded
TABLE 3-1:
PIN FUNCTION TABLE
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
Name
PDIP/SOIC Rotated
TSSOP/DFN TSSOP
Function
3.4
Serial Input (SI)
CS
SO
WP
1
2
3
3
4
5
Chip Select Input
Serial Data Output
Write-Protect Pin
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
V SS
4
6
Ground
3.5
Serial Clock (SCK)
SI
SCK
HOLD
V CC
5
6
7
8
7
8
1
2
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
The SCK is used to synchronize the communication
between a master and the 25XX256. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.1
Chip Select (CS)
3.6
Hold (HOLD)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
The HOLD pin is used to suspend transmission to the
25XX256 while in the middle of a serial sequence with-
out having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX256 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
3.2
Serial Output (SO)
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
The SO pin is used to transfer data out of the 25XX256.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
3.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
? 2007 Microchip Technology Inc.
DS21822F-page 13
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| 25LC256-IMFG | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:256K SPI Bus Serial EEPROM |
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