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SILICON POWER TRANSISTOR
2SB768
PNP SILICON TRIPLE DIFFUSED TRANSISTOR
DATA SHEET
Document No. D18264EJ4V0DS00 (4th edition)
(Previous No. TC-1625A)
Date Published July 2006 NS CP(K)
Printed in Japan
1985, 2006
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DESCRIPTION
The 2SB768 is designed for Color TV Vertical Deflection Output,
especially in Hybrid Integrated Circuits.
FEATURES
High Voltage: VCEO =
150 V
Complement to 2SD1033
ABSOLUTE MAXIMUM RATINGS (TA = 25
°C)
Collector to Base Voltage
VCBO
200
V
Collector to Emitter Voltage
VCEO
150
V
Emitter to Base Voltage
VEBO
5
V
Collector Current (DC)
IC(DC)
2
A
Collector Current (pulse)
Note 1
IC(pulse)
3
A
Total Power Dissipation (TA = 25
°C) Note 2
PT
2.0
W
Junction Temperature
Tj
150
°C
Storage Temperature
Tstg
55 to +150
°C
Notes 1. PW
≤ 10 ms, Duty Cycle ≤ 50%
2. When mounted on ceramic substrate of 7.5 cm
2 × 0.7 mm
PACKAGE DRAWING (Unit: mm)
12 3
4
6.5 ±0.2
4.4 ±0.2
5.0 ±0.2
0.5 ±0.1
5.6
±0.3
9.5
±0.5
2.5
±0.5
1.0
±0.5
1.5
0.1
+0.2
2.3 ±0.2
0.5 ±0.1
Note
0.4
MIN.
0.5
TYP.
0.15 ±0.15
2.3 ±0.3
5.5
±0.2
TO-252 (MP-3Z)
1. Base
2. Collector
3. Emitter
4. Collector Fin
Note The depth of notch at the top of the fin is
from 0 to 0.2 mm.
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