参数资料
型号: 405GPR
厂商: Applied Micro Circuits Corp.
英文描述: Power PC 405GPr Embedded Processor
中文描述: 405GPr的Power PC嵌入式处理器
文件页数: 21/57页
文件大小: 614K
代理商: 405GPR
405GPr – Power PC 405GPr Embedded Processor
28
AMCC
Revision 2.04 – September 7, 2007
Data Sheet
Signal List
The following table provides a summary of the number of package pins associated with each functional interface
group.
Multiplexed Pins
In the table “Signal Functional Description” on page 30, each external signal is listed along with a description of the
signal function. Some signals are multiplexed on the same pin (ball) so that the pin can be used for different
functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for
example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same function.
The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address
pins are used as outputs by the PPC405GPr to broadcast an address to external slave devices when the
PPC405GPr has control of the external bus. When, during the course of normal chip operation, an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC405GPr. In this example, the pins are also bidirectional, serving as both inputs
and outputs.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 51). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Pin Summary
Group
No. of Pins
PCI
60
Ethernet
18
SDRAM
71
External peripheral
96
External master
9
Internal peripheral
15
Interrupts
7
JTAG
5
System
18
Total Signal Pins
299
OVDD
32
VDD
24
Gnd
59
Thermal (and Gnd)
36
Reserved
6
Total Pins
456
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