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参数资料
| 型号： | 4421-DKDB2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 13/45页 |
| 文件大小： | 0K |
| 描述： | KIT DEV TEST EZRADIO SI4421 TRX |
| 标准包装： | 1 |
| 附件类型： | 测试卡，收发器，434MHz |
| 适用于相关产品： | EZRadio? |
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Si4421
CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands
consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-
bit command). Bits having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built-
in hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used to control the
nSEL pin to ensure the low level during the whole duration of the command or a software serial control interface should be
implemented. The Power-On Reset (POR) circuit sets default values in all control and command registers.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
? The TX register is ready to receive the next byte (RGIT)
? The RX FIFO has received the preprogrammed amount of bits (FFIT)
? Power-on reset (POR)
? RX FIFO overflow (FFOV) / TX register underrun (RGUR)
? Wake-up timer timeout (WKUP)
? Negative pulse on the interrupt input pin nINT (EXT)
? Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the RX FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To
identify the source of the IT, the status bits should be read out.
Timing Specification
Symbol
t CH
t CL
t SS
t SH
t SHI
t DS
t DH
t OD
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
Minimum value [ns]
25
25
10
10
25
5
5
10
Timing Diagram
nSEL
t SS
t SHI
t CH
t CL
t OD
t SH
SCK
t DS
t DH
SDI
SDO
BIT 15
FFIT
BIT 14
FFOV
BIT 13
BIT 8
CRL
BIT 7
AT S
BIT 1
OFFS(0)
BIT 0
FIFO OUT
13
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