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参数资料
| 型号： | 4421-DKDB2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 28/45页 |
| 文件大小： | 0K |
| 描述： | KIT DEV TEST EZRADIO SI4421 TRX |
| 标准包装： | 1 |
| 附件类型： | 测试卡，收发器，434MHz |
| 适用于相关产品： | EZRadio? |
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Si4421
INTERRUPT HANDLING
In order to achieve low power consumption there is an advanced event handling circuit implemented. The device has a very low
power consumption mode, so called sleep mode . In this mode only a few parts of the circuit are working. In case of an event, the
device wakes up, switches into active mode and an interrupt signal generated on the nIRQ pin to indicate the changed state to the
microcontroller. The cause of the interrupt can be determined by reading the status word of the device (see Status Read Command ,
page 27).
Several interrupt sources are available:
? RGIT – TX register empty interrupt: This interrupt generated when the transmit register is empty. Valid only when the el
(enable internal data register) bit is set in the Configuration Setting Command (page 15), and the transmitter is enabled in
the Power Management command.
? FFIT – the number of bits in the RX FIFO reached the preprogrammed level: When the number of received data bits in the
receiver FIFO reaches the threshold set by the f3…f0 bits of the FIFO and Reset Mode Command (page 20) an interrupt is
fired. Valid only when the ef (enable FIFO mode) bit is set in the Configuration Setting Command and the receiver is enabled
in the Power Management Command (page 15).
? POR – power on reset interrupt: An interrupt generated when the change on the VDD line triggered the internal reset circuit or
a software reset command was issued. For more details, see the Reset Modes section (page 34).
? RGUR – TX register under run: The automatic baud rate generator finished the transmission of the byte in the TX register
before the register write occurred. Valid only when the el (enable internal data register) bit is set in the Configuration Setting
Command and the transmitter is enabled in the Power Management command.
? FFOV – FIFO overflow: There are more bits received than the capacity of the FIFO (16 bits). Valid only when the ef (enable
FIFO mode) bit is set in the Configuration Setting Command and the receiver is enabled in the Power Management
command
? WKUP – wake-up timer interrupt: This interrupt event occurs when the time specified by the Wake-Up Timer Command (page
25) has elapsed. Valid only when the ew bit is set in the Power Management Command .
? EXT – external interrupt: Follows the level of the nINT pin if it is configured as an external Interrupt pin in the Receiver Control
Command (page 17, p16 bit is cleared).
? LBD – low battery detector interrupt: Occurs when the VDD goes below the programmable low battery detector threshold level
( v3…v0 bits in the Low Battery and Microcontroller Clock Divider Command , page 26). Valid only when the eb (enable low
battery detector) bit is set in the Power Management Command .
If any of the sources becomes active, the nIRQ pin will change to logic low level, and the corresponding bit in the status byte will be
HIGH.
Clearing an interrupt actually implies two things:
? Releasing the nIRQ pin to return to logic high
? Clearing the corresponding bit in the status byte
This may be completed with the following interrupt sources:
? RGIT: both the nIRQ pin and status bit remain active until the register is written (if under-run does not occur until the register
write), or the transmitter and the TX latch are switched off.
? FFIT: both the nIRQ pin and status bit remain active until the FIFO is read (a FIFO IT threshold number of bits have been
read), the receiver is switched off, or the RX FIFO is switched off.
? POR: both the nIRQ pin and status bit can be cleared by the read status command
? RGUR: this bit is always set together with RGIT; both the nIRQ pin and the status bit remain active until the transmitter and
the TX latch is switched off.
? FFOV: this bit is always set together with FFIT; it can be cleared by the status read command, but the FFIT bit and hence the
nIRQ pin will remain active until the FIFO is read fully, the receiver is switched off, or the RX FIFO is switched off.
? WKUP: both the nIRQ pin and status bit can be cleared by the read status command
? EXT: both the nIRQ pin and status bit follow the level of the nINT pin
? LBD: the nIRQ pin can be released by the reading the status, but the status bit will remain active while the VDD is below the
threshold.
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