参数资料
型号: 4450HA/3-K
厂商: EXAR CORP
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA324
封装: HSBGA-324
文件页数: 54/92页
文件大小: 780K
代理商: 4450HA/3-K
4450 – Data Sheet, DS-0131-06
Page 58
Hifn Confidential
Reset Capture functionality is defined immediately following the deassertion of the
hardware or software reset. The GPIO pins are latched on the deassertion of reset and the
subsequent latched state is used for the secondary (Reset Capture) functionality. The GPIO
may then be claimed for a Primary Use function following reset. The GPIO interface signals
are all referenced to supply voltage VDDE.
.
Boot Configuration
During the boot process, the DPU reads the dpu_gpio[1]/boot_config_1 and
dpu_gpio[0]/boot_config_0 pins to determine how the boot process will occur. A resistor
should be used to pull the boot_config_0 and boot_config_1 pins high or low during the
boot phase. Using a resistor rather than directly tying this pin allows allows dpu_gpio[1]
and dpu_gpio[0] to be used as general purpose I/O for other user defined function during
normal operation after the boot process completes.
boot_config_1 - Flash Indicator. If asserted high indicates the presence of a Flash device
connected to esc_gpio[4:0].
boot_config_0 - Secure Boot Mode. If asserted low allows booting from a Flash, the Host
0 GMAC Interface, or the RMII Control Interface. If asserted high, the 4450 will boot from
either a Flash or the RMII Control Interface.
Status Indicators (Optional)
Table 6-22. General Purpose I/O Pins
Signal Name
I/O
Type
Primary Use
Reset Capture
Reset Capture Function
dpu_gpio[7]
I/O
DPU Status
Not Available
dpu_gpio[6]
I/O
MDIO/SDA
Not Available
dpu_gpio[5]
I/O
MDC/SCL
ddr_config_2
1=enable ODT, 0=no ODT
dpu_gpio[4]
I/O
Net0 TX_DISABLE
ddr_config_1
dpu_gpio[3]
I/O
Net1 TX_DISABLE
ddr_config_0
dpu_gpio[2]
I/O
Net0 RX_LOSS
RGMII/RTBI
Voltage Level
1=1.5V HSTL, 0=2.5V LVCMOS
dpu_gpio[1]
I/O
Net1 RX_LOSS
boot_config_1
1=Flash, 0=No Flash
dpu_gpio[0]
I/O
unassigned
boot_config_0
1= Secure Boot, 0=Normal Boot
esc_gpio[7]
I/O
eSC Status
Not Available
esc_gpio[6]
I/O
PHY Interrupt
Device_ID[2]
esc_gpio[5]
I/O
unassigned
Device_ID[1]
esc_gpio[4]
I/O
eSC_Flash_CS1
Device_ID[0}
esc_gpio[3]
I/O
eSC_Flash_SO
RMII MAC/PHY
1=PHY, 0=MAC
esc_gpio[2]
I/O
eSC_Flash_SI
100M/1G Boot
1= 100M boot, 0= 1G boot
esc_gpio[1]
I/O
eSC_Flash_CLK
unassigned
esc_gpio[0]
I/O
eSC_Flash_CS0
Not Available
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