参数资料
型号: 4450HA/3-K
厂商: EXAR CORP
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA324
封装: HSBGA-324
文件页数: 58/92页
文件大小: 780K
代理商: 4450HA/3-K
4450 – Data Sheet, DS-0131-06
Page 61
Hifn Confidential
When the network ports are connected to a fiber optic PHY or an SFP module, the
Transmitter Enable (TX EN) and Signal Detect (SigDet) signals from the PHY may be
connected to the 4450 so that the optional Station Management (STM) software can
manage these signals. There are two GPIO's assigned to this function for Network port 0
and two more for Network port 1.
Note that within the 4450, these signals have no direct impact on the data flow through the
device. The SigDet signal(s) are simply monitored by the STM server and the state reported
to the host. The TX EN signal(s) are driven out to the PHY by the STM server under
command of the host.
Other GPIO Functionality (Optional)
Some of the remaining GPIO pins may have other Primary or Secondary (Reset Capture)
uses defined after reset. Additional information on alternate functionality of the GPIO pins
will be provided on a subsequent release of the data sheet.
6.8 Miscellaneous Pins
Table 6-24. Test and mode signal pins
Signal Name
I/O Type
Description
por_n
Input
Power-on-reset, active low
host_config[2:0
]
Input
Configures the operating modes of the two Host-side GMAC
data interfaces, as follows:
Host Side
MAC/PHY
000:
RGMII
MAC or PHY
001:
RTBI
MAC or PHY
010:
SGMII
MAC or PHY
011:
SerDes
MAC or PHY
100:
GMII
MAC
101:
GMII
PHY
110:
TBI
MAC
111:
TBI
PHY
net_config[1:0]
Input
Configures the operating modes of the two Network-side GMAC
data interfaces, as follows:
Network Side
MAC/PHY
00:
RGMII
MAC or PHY
01:
RTBI
MAC or PHY
10:
SGMII
MAC or PHY
11:
SerDes
MAC or PHY
testmode
Input
Hifn internal test input. Tie low for normal operation.
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