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参数资料
| 型号： | 45IZ |
| 厂商： | Intersil Corporation |
| 英文描述： | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | 单5V或12V同步降压脉宽调制（PWM）控制器 |
| 文件页数： | 12/16页 |
| 文件大小： | 302K |
| 代理商： | 45IZ |
www.DataSheet4U.com
5
FN6305.3
November 15, 2006
Functional Pin Description (SOIC,DFN)
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545, as well as
the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if VCC rises above 6.5V (but the LGATE/OCSET and
BOOT will still be sourced by VCC). Connect a well-
decoupled 5V or 12V supply to this pin.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package, Pin
4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-channel MOSFET (equal to VCC minus
the on-chip BOOT diode voltage drop), with respect to PHASE.
COMP/SD (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (VDISABLE = 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external pull-
down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20A
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20A charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the VDISABLE trip point, the
ISL6545 will begin a new Initialization and soft-start cycle.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from VCC). This pin is also
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (ROCSET) from this pin to GND. See the
Overcurrent Protection section for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
Lower Gate Sink Impedance
RLG-SNKh
VCC = 14.5V; I = 50mA
-
2.0
-
Ω
Upper Gate Source Impedance
RUG-SRCl
VCC = 4.25V; I = 50mA
-
3.5
-
Ω
Upper Gate Sink Impedance
RUG-SNKl
VCC = 4.25V; I = 50mA
-
2.7
-
Ω
Lower Gate Source Impedance
RLG-SRCl
VCC = 4.25V; I = 50mA
-
2.75
-
Ω
Lower Gate Sink Impedance
RLG-SNKl
VCC = 4.25V; I = 50mA
-
2.1
-
Ω
PROTECTION/DISABLE
OCSET Current Source
IOCSET
ISL6545C; LGATE/OCSET = 0V
19.5
21.5
23.5
μA
ISL6545I; LGATE/OCSET = 0V
18.0
21.5
23.5
μA
Disable Threshold (COMP/SD pin)
VDISABLE
0.375
0.400
0.425
V
Electrical Specifications
Test Conditions: VCC = 12V, TJ = 0 to 85°C, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6545, ISL6545A
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