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| 型号： | 4610M-901-103 |
| 英文描述： | KONDENSATOR NETZWERK |
| 中文描述： | KONDENSATOR NETZWERK |
| 文件页数： | 51/62页 |
| 文件大小： | 1883K |
| 代理商： | 4610M-901-103 |
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Specifications are subject to change without notice.
331
Use Bourns Networks To:
Match impedance between memory driver and the DRAM
array.
Minimize reflections and ringing in DRAM inputs.
Prevent undershoot of RAS, CAS, and WE signals which
may result in latch-up of DRAM inputs
Improve system performance by allowing faster setting
times for DRAM inputs.
Need For Damping
The address lines (RAS, CAS) and control lines (WE) of
dynamic RAM arrays are driven in parallel, causing significant
loading on the driver of the DRAM arrays. Each DRAM control
input (WE) has capacitive loading between 5pF to 7pF, while
each address line input has about a 10pF load.
Thus each DRAM input can be modeled as a transmission line
with distributed inductance and capacitance. If not properly ter-
minated, signal reflections and ringing on the line will result,
adversely affecting the performance of the memory system. The
effects on signal transitions will be:
1. Increased settling time delay on low-to-high transitions.
2. Voltage undershoot on high-to-low transitions.
Increased settling time due to ringing reduces system perfor-
mance because the design has to allow for the settling delay
before sampling the signal. Undershoot, by bringing the input
voltage below 0 volts, can damage the driver IC as well as alter
the DRAM’s internal address register contents, causing potential
loss of data.
TIMING
REFERENCE
MEMORY
CONTROL
DATA
SYSTEM DATA BUS
TIMING
CONTROLLERS
DATA
CPU
ADDRESS
DYNAMIC
MEMORY
CONTROL
ADDRESS
RAS
CAS
WE
DYNAMIC
MEMORY
ARRAY
BLOCK DIAGRAM OF DRAM SYSTEM
EFFECT OF DAMPING RESISTOR
WITHOUT
DAMPING
RESISTOR
WITH
DAMPING
RESISTOR
Courtesy of B. Narasimhan and J. Shaffer, Micron Techology Corporation.
t1
t2
1
V
"HIGH"
LOGIC
LEVEL
COMPARISON OF UNDERSHOOTS
WITHOUT
DAMPING RESISTOR
WITH
DAMPING RESISTOR
t1 - TIME TO ACCEPTABLE "LOW" LOGIC LEVEL FOR
DRIVER WITHOUT DAMPING RESISTOR
t2 - TIME TO ACCEPTABLE "LOW" LOGIC
LEVEL WITHDAMPING RESISTOR
DRAM Applications
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 4610M-901-103LF | 功能描述:电容器阵列与网络 10Pin 0.01uF 20% Bussed X7R RoHS:否 制造商:AVX 电容:0.1 uF 容差:20 % 电压额定值:6.3 V 元件数量:2 工作温度范围: 外壳长度:0.8 mm 外壳宽度:1.6 mm 外壳高度:0.5 mm 端接类型:SMD/SMT 系列:PG |
| 4610M-901-104 | 功能描述:电容器阵列与网络 10Pin 0.1uF 20% Bussed X7R RoHS:否 制造商:AVX 电容:0.1 uF 容差:20 % 电压额定值:6.3 V 元件数量:2 工作温度范围: 外壳长度:0.8 mm 外壳宽度:1.6 mm 外壳高度:0.5 mm 端接类型:SMD/SMT 系列:PG |
| 4610M-901-104LF | 功能描述:电容器阵列与网络 10Pin 0.1uF 20% Bussed X7R RoHS:否 制造商:AVX 电容:0.1 uF 容差:20 % 电压额定值:6.3 V 元件数量:2 工作温度范围: 外壳长度:0.8 mm 外壳宽度:1.6 mm 外壳高度:0.5 mm 端接类型:SMD/SMT 系列:PG |
| 4610M-901-104LF | 制造商:Bourns Inc 功能描述:CAPACITOR ARRAY 0.1UF 50V X7R SIP 制造商:Bourns Inc 功能描述:CAPACITOR, ARRAY, 0.1UF, 50V, X7R, SIP |
| 4610M-901-104LF | 制造商:Bourns Inc 功能描述:CAPACITOR NETWORK 0.1UF ((NW)) |
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