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参数资料
| 型号： | 48SD1616RPFH |
| 厂商： | MAXWELL TECHNOLOGIES |
| 元件分类： | DRAM |
| 英文描述： | 256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks |
| 中文描述： | 16M X 16 SYNCHRONOUS DRAM, 6 ns, DFP72 |
| 封装： | DFP-72 |
| 文件页数： | 2/42页 |
| 文件大小： | 596K |
| 代理商： | 48SD1616RPFH |
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48SD1616
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10
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
01.07.05 REV 4
DQMU/DQML Truth Table
Note: H: V
IH L: VIL x VIH or VIL
Write: I
DID is Needed
Read: I
DOD is Needed
The SDRAM can mask input/output data by means of DQMU/DQML.
DQMU masks the upper byte and DQML masks the lower byte.
During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On
the other hand, when DQMU/DQML is set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the
previous data is held ( the new data is not written). Desired data can be masked during burst read or burst
write by setting DQMU/DQML. For more details, refer to the DQMU/DQML control section of the SDRAM
operating instructions.
COMMAND
SYMBOL
CKE=N-1
CKE=N
DQMU
DQML
Upper byte (DQ8 to DQ15) write enable/out-
put enable
ENBU
H
x
L
x
Lower byte (DQ0 to DQ7) write enable/out-
put enable
ENBL
H
x
L
Upper byte (DQ8 to DQ15) write inhibit/out-
put disable
MASKU
H
x
H
x
Lower byte (DQ0 to DQ7) write inhibit/out-
put disable
MASKL
H
x
H
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 48SD1616RPFI | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks |
| 48SD1616RPFK | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks |
| 48SD3208 | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFE | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFH | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
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