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| 型号： | 5962-8768102VEA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 1180 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 13/15页 |
| 文件大小： | 503K |
| 代理商： | 5962-8768102VEA |
LEADING EDGE BLANKING
t
LEB + 0.5
R
10 kW
C
(2)
UDG-95105
UVLO, SOFT-START AND FAULT MANAGEMENT
www.ti.com ..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
The UC1825A performs fixed frequency pulse width modulation control. The UC1825A outputs are alternately
controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator
frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output is driven high. The end of the pulse is
controlled by the PWM comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates
the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time
after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The
PWM ramp input may not require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set
by C and the internal 10-k
resistor determines the blanked interval. The 10-k resistor has a 10% tolerance.
For more accuracy, an external 2-k
1% resistor (R) can be added, resulting in an equivalent resistance of
1.66 k
with a tolerance of 2.4%. The design equation is:
Values of R less than 2 k
should not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V
threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic
overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the
outputs driven low. For this reason, some noise filtering may be required on the ILIM pin.
Figure 4. Leading Edge Blanking Operational Waveforms
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error
amplifier output is also forced low. While the internal 9-
A source charges the SS pin, the error amplifier output
follows until closed loop regulation takes over.
Copyright 2009, Texas Instruments Incorporated
7
Product Folder Link(s): UC1825A-SP
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