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参数资料
| 型号： | 5962D1022901QXC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封装： | CERAMIC, QFP-128 |
| 文件页数： | 16/68页 |
| 文件大小： | 1475K |
| 代理商： | 5962D1022901QXC |
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may
be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O
contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the
WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13. The DQM signal must be asserted (HIGH) at
least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ.
After the WRITE command is registered, the DQs go High-Z (or remain High-Z), regardless of the state of the DQM signal,
provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 13, then the WRITEs at T5 and T7 would
be valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the
written data is not masked. Figure 12 shows the case where the clock frequency allows for bus contention to be avoided without add-
ing a NOP cycle, and Figure 13 shows the case where the additional NOP is needed.
Figure 12: READ-to-WRITE
READ
NOP
WRITE
BANK
Dout n
Din b
T5
T4
T3
T2
T1
T0
tHZ
tDS
tCK
Notes:
1.
CL = 3 is used for illustration. The READ or WRITE Command may be to any bank.
CLK
DQM
Command
Address
DQ
If a burst of one is used, DQM is not required.
Don’t Care
Transitioning Data
COL n
BANK
COL b
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相关代理商/技术参数 |
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| 5962D9563201VXC | 制造商:STMicroelectronics 功能描述:RS-432LINE DRIVERQUADFLAT16, GOLD - Bulk |
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