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参数资料
| 型号： | 5962R0722701VZA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDSO16 |
| 封装： | CERAMIC, SOIC-16 |
| 文件页数： | 10/22页 |
| 文件大小： | 510K |
| 代理商： | 5962R0722701VZA |
2.0 Applications Information
2.1 TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 8. The split analog and
digital supply pins are both powered in this example by the
National LP2950 low-dropout voltage regulator. The analog
supply is bypassed with a capacitor network located close to
the ADC128S102. The digital supply is separated from the
analog supply by an isolation resistor and bypassed with ad-
ditional capacitors. The ADC128S102 uses the analog supply
(V
A) as its reference voltage, so it is very important that VA be
kept as clean as possible. Due to the low power requirements
of the ADC128S102, it is also possible to use a precision ref-
erence as a power supply.
30018113
FIGURE 8. Typical Application Circuit
2.2 POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this prod-
uct: power supply sequencing, power management, and the
effect of digital supply noise on the analog supply.
2.2.1 Power Supply Sequence
The ADC128S102 is a dual-supply device. The two supply
pins share ESD resources, so care must be exercised to en-
sure that the power is applied in the correct sequence. To
avoid turning on the ESD diodes, the digital supply (V
D) can-
not exceed the analog supply (V
A) by more than 300 mV,
during a conversion cycle. Therefore, V
A must ramp up before
or concurrently with V
D.
2.2.2 Power Management
The ADC128S102 is fully powered-up whenever CS is low
and fully powered-down whenever CS is high, with one ex-
ception. If operating in continuous conversion mode, the AD-
C128S102 automatically enters power-down mode between
SCLK's 16th falling edge of a conversion and SCLK's 1st
falling edge of the subsequent conversion (see Figure 1).
In continuous conversion mode, the ADC128S102 can per-
form multiple conversions back to back. Each conversion
requires 16 SCLK cycles and the ADC128S102 will perform
conversions continuously as long as CS is held low. Contin-
uous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power
consumption by performing fewer conversions per unit time.
This means spending more time in power-down mode and
less time in normal mode. By utilizing this technique, the user
can achieve very low sample rates while still utilizing an SCLK
frequency within the electrical specifications. The Power Con-
sumption vs. SCLK curve in the Typical Performance Curves
section shows the typical power consumption of the AD-
C128S102. To calculate the power consumption (P
C), simply
multiply the fraction of time spent in the normal mode (t
N) by
the normal mode power consumption (P
N), and add the frac-
tion of time spent in shutdown mode (t
S) multiplied by the
shutdown mode power consumption (P
S) as shown in Figure
30018115
FIGURE 9. Power Consumption Equation
2.2.3 Power Supply Noise Considerations
The charging of any output load capacitance requires current
from the digital supply, V
D. The current pulses required from
the supply to charge the output capacitance will cause voltage
variations on the digital supply. If these variations are large
enough, they could degrade SNR and SINAD performance of
the ADC. Furthermore, if the analog and digital supplies are
tied directly together, the noise on the digital supply will be
coupled directly into the analog supply, causing greater per-
formance degradation than would noise on the digital supply
alone. Similarly, discharging the output capacitance when the
digital output goes from a logic high to a logic low will dump
current into the die substrate, which is resistive. Load dis-
charge currents will cause "ground bounce" noise in the sub-
strate that will degrade noise performance if that current is
large enough. The larger the output capacitance, the more
current flows through the die substrate and the greater the
noise coupled into the analog channel.
The first solution to keeping digital noise out of the analog
supply is to decouple the analog and digital supplies from
each other or use separate supplies for them. To keep noise
out of the digital supply, keep the output load capacitance as
small as practical. If the load capacitance is greater than 50
pF, use a 100
series resistor at the ADC output, located as
close to the ADC output pin as practical. This will limit the
charge and discharge current of the output capacitance and
improve noise performance. Since the series resistor and the
www.national.com
18
ADC128S102QML
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