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| 型号： | 5962R0722701VZA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDSO16 |
| 封装： | CERAMIC, SOIC-16 |
| 文件页数： | 9/22页 |
| 文件大小： | 510K |
| 代理商： | 5962R0722701VZA |
condition, the ADC automatically enters track mode and the
falling edge of CS is seen as the first falling edge of SCLK. In
the third condition, CS and SCLK go low simultaneously and
the ADC enters track mode. While there is no timing restriction
with respect to the falling edges of CS and SCLK, see Figure
3 for setup and hold time requirements for the falling edge of
CS with respect to the rising edge of SCLK.
During each conversion, data is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after
the fall of CS. The control register is loaded with data indicat-
ing the input channel to be converted on the subsequent
conversion (see Tables 1, 2, 3).
Although the ADC128S102 is able to acquire the input signal
to full resolution in the first conversion immediately following
power-up, the first conversion result after power-up will be
that of a randomly selected channel. Therefore, the user
needs to incorporate a dummy conversion to set the required
channel that will be used on the subsequent conversion.
TABLE 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
ADD2
ADD1
ADD0
DONTC
TABLE 2. Control Register Bit Descriptions
Bit #:
Symbol:
Description
7, 6, 2, 1, 0
DONTC
Don't care. The values of these bits do not affect the device.
5
ADD2
These three bits determine which input channel will be sampled and converted
at the next conversion cycle. The mapping between codes and channels is
shown in Table 3.
4
ADD1
3
ADD0
TABLE 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
0
IN0
0
1
IN1
0
1
0
IN2
0
1
IN3
1
0
IN4
1
0
1
IN5
1
0
IN6
1
IN7
1.3 ADC128S102 TRANSFER FUNCTION
The output format of the ADC128S102 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC128S102 is V
A / 4096.
The ideal transfer characteristic is shown in Figure 6. The
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of V
A / 8192.
Other code transitions occur at steps of one LSB.
30018111
FIGURE 6. Ideal Transfer Characteristic
1.4 ANALOG INPUTS
An equivalent circuit for one of the ADC128S102's input chan-
nels is shown in Figure 7. Diodes D1 and D2 provide ESD
protection for the analog inputs. The operating range for the
analog inputs is 0 V to V
A. Going beyond this range will cause
the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 7 has a typical value of 3 pF and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch and is
typically 500 ohms. Capacitor C2 is the ADC128S102 sam-
pling capacitor, and is typically 30 pF. The ADC128S102 will
deliver best performance when driven by a low-impedance
source (less than 100 ohms). This is especially important
when using the ADC128S102 to sample dynamic signals. Al-
so important when sampling dynamic signals is a band-pass
or low-pass filter which reduces harmonics and noise in the
input. These filters are often referred to as anti-aliasing filters.
30018114
FIGURE 7. Equivalent Input Circuit
1.5 DIGITAL INPUTS AND OUTPUTS
The ADC128S102's digital inputs (SCLK, CS, and DIN) have
an operating range of 0 V to V
A. They are not prone to latch-
up and may be asserted before the digital supply (V
D) without
any risk. The digital output (DOUT) operating range is con-
trolled by V
D. The output high voltage is VD - 0.5V (min) while
the output low voltage is 0.4V (max).
17
www.national.com
ADC128S102QML
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