参数资料
型号: 5962R9675501VJX
厂商: INTERSIL CORP
元件分类: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CDIP24
封装: SIDE BRAZED, DIP-24
文件页数: 4/7页
文件大小: 125K
代理商: 5962R9675501VJX
4
specication given is the larger of the two, representing
worst case drift.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -
15V or +15V supplies. It is specied under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specied accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
Applying the HS-565ARH
OP AMP Selection
The HS-565ARH’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplier should be
reviewed for each application, since a signicant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplier combination is
where tD, tA are settling times for the DAC and amplier.
No Trim Operation
The HS-565ARH will perform as specied without calibration
adjustments. To operate without calibration, substitute 50
resistors for the 100
trimming potentiometers: In Figure 1
replace R2 with 50
; also remove the network on pin 8 and
connect 50
to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50
resistors.
With these changes, performance is guaranteed as shown
under Specications, “External Adjustments”. Typical
unipolar zero will be
±0.50 LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
t
D
()2
t
A
()2
+
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565ARH
3K
3.5K
19.95
K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R2
100
8
BIP.
OFF.
+15V
-15V
R1
50k
100k
100
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565ARH
3K
3.5K
19.95K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R4
100
8
BIP.
OFF.
R3
100
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
HS-565ARH
相关PDF资料
PDF描述
5962R9675501VJX PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CDIP24
5962R9675501VXX PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CQFP24
59643-1 BAND PASS FILTER
59643-2 BAND PASS FILTER
F4319 BAND PASS FILTER
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