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| 型号： | 5M80ZT100I5N |
| 厂商： | Altera |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC MAX V CPLD 80 LE 100-TQFP |
| 产品培训模块： | Max V Overview |
| 特色产品： | MAX? V CPLDs |
| 标准包装： | 90 |
| 系列： | MAX® V |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 1.71 V ~ 1.89 V |
| 逻辑元件/逻辑块数目： | 80 |
| 宏单元数： | 64 |
| 输入/输出数： | 79 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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Chapter 3: DC and Switching Characteristics for MAX V Devices
3–11
Timing Model and Specifications
Preliminary and Final Timing
This section describes the performance, internal, external, and UFM timing
specifications. All specifications are representative of the worst-case supply voltage
and junction temperature conditions.
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary. Table 3–16 lists the status of the MAX V device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 3–16. Timing Model Status for MAX V Devices
Device
5M40Z
5M80Z
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
Final
v
v
v
v
v
v
v
Performance
performance values were obtained with the Quartus II software compilation of
megafunctions.
Table 3–17. Device Performance for MAX V Devices (Part 1 of 2)
Performance
Resource
Used
Design Size and
Function
Resources Used
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
Unit
Mode
LEs
UFM
Blocks
C4
C5, I5
C4
C5, I5
16-bit counter (1)
64-bit counter (1)
16-to-1 multiplexer
—
—
—
16
64
11
0
0
0
184.1
83.2
17.4
118.3
80.5
20.4
247.5
154.8
8.0
201.1
125.8
9.3
MHz
MHz
ns
LE
32-to-1 multiplexer
16-bit XOR function
16-bit decoder with
single address line
—
—
—
24
5
5
0
0
0
12.5
9.0
9.2
25.3
16.1
16.1
9.0
6.6
6.6
11.4
8.2
8.2
ns
ns
ns
May 2011
Altera Corporation
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