参数资料
型号: 5M80ZT100I5N
厂商: Altera
文件页数: 17/30页
文件大小: 0K
描述: IC MAX V CPLD 80 LE 100-TQFP
产品培训模块: Max V Overview
特色产品: MAX? V CPLDs
标准包装: 90
系列: MAX® V
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 1.71 V ~ 1.89 V
逻辑元件/逻辑块数目: 80
宏单元数: 64
输入/输出数: 79
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 100-TQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
3–17
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
Symbol
Parameter
C4
C5, I5
C4
C5, I5
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Minimum erase signal
t AE
to address clock hold
0
0
0
0
ns
time
Maximum delay between
t EB
the erase rising edge to
the UFM busy signal
960
960
960
960
ns
rising edge
Minimum delay allowed
t BE
from the UFM busy
signal going low to
20
20
20
20
ns
erase signal going low
t EPMX
Maximum length of busy
pulse during an erase
500
500
500
500
ms
Delay from data register
t DCO
clock to data register
5
5
5
5
ns
output
Delay from OSC_ENA
t OE
signal reaching UFM to
rising clock of OSC
180
180
180
180
ns
leaving the UFM
t RA
Maximum read access
time
65
65
65
65
ns
Maximum delay between
t OSCS
the OSC_ENA rising edge
to the erase/program
250
250
250
250
ns
signal rising edge
Minimum delay allowed
from the
t OSCH
erase/program signal
250
250
250
250
ns
going low to OSC_ENA
signal going low
May 2011
Altera Corporation
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