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Rabbit 3000 Microprocessor User’s Manual
Watchdog Timer Control Register
(WDTCR)
(Address = 0x0008)
Bit(s)
Value
Description
7:0
0x005A
Restart the watchdog timer with a 2-second timeout period.
0x0057
Restart the watchdog timer with a 1-second timeout period.
0x0059
Restart the watchdog timer with a 500 ms timeout period.
0x0053
Restart the watchdog timer with a 250 ms timeout period.
0x005F
Restart the secondary watchdog timer (starting with Rabbit 3000A chip).
other
No effect on watchdog timer or secondary watchdog timer.
Watchdog Timer Test Register
(WDTTR)
(Address = 0x0009)
Bit(s)
Value
Description
7:0
0x0051
Clock the least significant byte of the watchdog timer from the peripheral clock.
(Intended for chip test and code 0x0054 below only.)
0x0052
Clock the most significant byte of the watchdog timer from the peripheral clock.
(Intended for chip test and code 0x0054 below only.)
0x0053
Clock both bytes of the watchdog timer, in parallel, from the peripheral clock.
(Intended for chip test and code 0x0054 below only.)
0x0054
Disable the watchdog timer. This value, by itself, does not disable the watchdog
timer. Only a sequence of two writes, where the first write is 0x0051, 0x0052, or
0x0053, followed by a write of 0x0054, actually disables the watchdog timer.
The watchdog timer will be re-enabled by any other write to this register.
other
Normal clocking (32 kHz oscillator) for the watchdog timer. This is the condition
after reset.
Secondary Watchdog Timer Register
(SWDTR)
(Address = 0x000C)
Bit(s)
Value
Description
7:0
The time constant for the secondary watchdog timer is stored. This time constant
will take effect the next time that the secondary watchdog counter counts down
to zero. The timer counts modulo n + 1, where n is the programmed time constant.
The secondary watchdog timer can be disabled by writing the sequence 0x005A
– 0x0052 – 0x0044 to this register.