49
Data Segment Register
(DATASEG)
(Address = 0x0012)
Bit(s)
Value
Description
7:0
Read
The current contents of this register are reported.
Write
Eight LSBs (MSBs are set to zero by write) of physical address offset to use if:
SEGSIZ[3:0]
Addr[15:12] < SEGSIZ[7:4]
Segment Size Register
(SEGSIZ)
(Address = 0x0013)
Bit(s)
Value
Description
7:0
Read
The current contents of this register are reported.
7:4
Write
Boundary value for switching from DATASEG to STACKSEG for translation.
3:0
Write
Boundary value for switching from none to DATASEG for translation.
Memory Bank x Control Register
(MB0CR)
(Address = 0x0014)
(MB1CR)
(Address = 0x0015)
(MB2CR)
(Address = 0x0016)
(MB3CR)
(Address = 0x0017)
Bit(s)
Value
Description
7:6
00
Four (five for writes) wait states for accesses in this bank.
01
Two (three for writes) wait states for accesses in this bank.
10
One (two for writes) wait states for accesses in this bank.
11
Zero (one for writes) wait states for accesses in this bank.
5
0
Pass bank select address MSB for accesses in this bank.
1
Invert bank select address MSB for accesses in this bank.
4
0
Pass bank select address LSB for accesses in this bank.
1
Invert bank select address LSB for accesses in this bank.
3:2
00
/OE0 and /WE0 are active for accesses in this bank.
01
/OE1 and /WE1 are active for accesses in this bank.
10
/OE0 only is active for accesses in this bank (i.e., read-only). Transactions are
normal in every other way.
11
/OE1 only is active for accesses in this bank (i.e., read-only). Transactions are
normal in every other way.
1:0
00
/CS0 is active for accesses in this bank.
01
/CS1 is active for accesses in this bank.
10
/CS2 is active for accesses in this bank.
11
This bit combination is reserved and should not be used.