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| 型号： | 71M6531D-IMR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 30/121页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 128KB 68-QFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | * |
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
1.4.8
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see 1.5.16
1.4.9
Interrupts
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register ( TCON , IRCON and SCON ). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0 (SFR 0xA8),
IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 8 shows the device interrupt structure.
Referring to Figure 8 , interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M653x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 8 , and in Table 24 and
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36 . Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to
the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt
will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following
conditions are met:
?
?
?
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0 , IEN1 , IEN2 , IP0 or IP1 .
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
?
?
?
?
The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28 ).
The interrupt request register, IRCON (see Table 29 ).
The interrupt priority registers: IP0 and IP1 (see Table 34 ).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
IEN0[7]
Symbol
EAL
EAL = 0 disables all interrupts.
Function
30
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
WDT
–
ES0
ET1
EX1
ET0
EX0
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1.
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0.
Rev 2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6531F | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Energy Meter IC |
| 71M6531F-DB | 功能描述:开发板和工具包 - 8051 71M6531F Demo Brd RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
| 71M6531F-IM/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IM/F3 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IM/F4 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
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