参数资料
型号: 71M6531F-IMR/F
厂商: Maxim Integrated
文件页数: 33/121页
文件大小: 0K
描述: IC ENERGY METER 256KB 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: *
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Interrupt Enable
Name Location
Interrupt Flag
Name Location
Interrupt Description
AUTOWAKE flag
PB flag
EX4
EX5
EX6
EX_XFER
EX_RTC
IEN_WD_NROVF
IEN_SPI
EX_FWCOL
EX_PLL
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
2002[1]
20B0[0]
20B0[4]
2007[4]
2007[5]
IEX4
IEX5
IEX6
IE_XFER
IE_RTC
WD_NROVF_FLAG
SPI_FLAG
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
20B1[0]
20B1[4]
SFR E8[3]
SFR E8[2]
SFR E8[6]
SFR E8[7]
SFR E8[5]
SFR E8[4]
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
FWCOL0 interrupt (INT 2)
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
?
?
The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
?
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
WD_NROVF_FLAG is set approximately 1 ms before a WDT reset occurs. The flag can be cleared by writ-
ing a zero to it and is automatically cleared by the falling edge of WAKE.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32 :
Table 32: Interrupt Priority Level Groups
Group
0
1
2
3
4
5
Group Members
External interrupt 0, Serial channel 1 interrupt
Timer 0 interrupt, External interrupt 2
External interrupt 1, External interrupt 3
Timer 1 interrupt, External interrupt 4
Serial channel 0 interrupt, External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1 ( Table 34 ).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
Rev 2
IP1 [x]
0
0
1
1
IP0 [x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
33
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