参数资料
型号: 71M6531F-IMR/F
厂商: Maxim Integrated
文件页数: 79/121页
文件大小: 0K
描述: IC ENERGY METER 256KB 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: *
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Name
Location
Reset
Wake
Dir
Description
When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes
SDCK and DIO5 becomes bi-directional SDATA.
DIO_EEX[1:0]
Function
DIO_EEX[1:0]
2008[7:6]
0
0
R/W
00
Disable EEPROM interface
01
10
11
2-Wire EEPROM interface
3-Wire EEPROM interface
not used
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
2008[2]
2008[3]
200F[3]
200F[2]
SFR 9E
SFR 9F
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Causes VARPULSE to be output on DIO7.
Causes WPULSE to be output on DIO6.
Causes XPULSE to be output on DIO8.
Causes YPULSE to be output on DIO9.
Serial EEPROM interface data.
Serial EEPROM interface control.
Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
ECK_DIS
EQU[2:0]
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
2005[5]
2000[7:5]
2002[0]
2002[1]
2007[4]
2007[5]
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
Specifies the power equation to be used by the CE.
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9
Interrupts for details.
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls
the time taken for each conversion.
[M40MHZ, M26MHZ]
FIR_LEN[1:0]
Resulting FIR
Filter Cycles
Resulting
CK32 Cycles
Resulting
DC Gain
FIR_LEN[1:0]
2007[3:2]
1
1
R/W
[00], [10], or [11]
00
01
138
288
1
2
0.110017
1.000
10
384
3
2.37037
[01]
00
01
10
186
384
588
1
2
3
0.113644
1.000
3.590363
FL_BANK[2:0]
SFR B6[2:0]
1
1
R/W
Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
Rev 2
79
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