参数资料
型号: 71M6541F-IGTR/F
厂商: Maxim Integrated
文件页数: 17/166页
文件大小: 0K
描述: IC ENERGY METER SGL PHSE 64LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: Single Converter Technology®
输入阻抗: 40 千欧 ~ 90 千欧
测量误差: 0.5%
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电流 - 电源: 4mA
电源电压: 3 V ~ 3.6 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 标准包装
其它名称: 71M6541F-IGTR/FDKR
71M6541D/F/G and 71M6542F/G Data Sheet
processed with locally connected sensors, as shown in Figure 3 . When using one local and one remote
sensor ( Figure 5 ), the multiplexer sequence is also as shown in Figure 7 .
For both multiplexer sequences shown in Figure 6 and Figure 7 , the frame duration is 13 CK32 cycles
(where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.
Table 3 summarizes the various AFE input configurations.
Multiplexer Frame
CK32
MUX_DIV[3:0] = 3 Conversions
Settle
MUX STATE S
Fig. 2:
Fig. 3:
Fig. 5:
0
IA
IA
IA
1
VA
VA
VA
2
IB
Not Used
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 6: States in a Multiplexer Frame ( MUX_DIV[3:0] = 3)
Multiplexer Frame
CK32
MUX_DIV = 4 Conversions
Settle
MUX STATE S
Fig. 4:
0
IA
1
VA
2
IB
3
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 7: States in a Multiplexer Frame ( MUX_DIV[3:0] = 4)
Table 3: ADC Input Configuration
Pin
IAP
IAN
IBP
ADC
Channel
ADC0
ADC1
ADC2
Required
Setting
DIFFA_E = 1
Comment
Differential mode must be selected with DIFFA_E = 1 ( I/O
RAM 0x210C[4] ). The ADC results are stored in CE RAM
location ADC0 ( CE RAM 0x0 ), and ADC1 ( CE RAM 0x1 ) is not
disturbed.
For locally connected sensors ( Figure 2 and Figure 4 ), the
differential input must be enabled by setting DIFFB_E (I/O
RAM 0x210C[5] .
DIFFB_E = 1 For the remote connected sensor ( Figure 3 and Figure 5 )
or
with a remote shunt sensor, RMT_E ( I/O RAM 0x2709[3] )
IBN
ADC3
RMT_E = 1
must be set.
In both cases, the ADC results are stored in RAM location
ADC2 (CE RAM 0x2) , and ADC3 (CE RAM 0x3) is not
disturbed.
VA
VB
ADC10
ADC9
--
--
Single-ended mode only. The ADC result is stored in RAM
location ADC10 ( CE RAM 0xA ).
Single-ended mode only (71M6542F only). The ADC result
is stored in RAM location ADC9 ( CE RAM 0x9 ).
Rev 4
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