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参数资料
| 型号： | 72825LB15PFI9 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 14/26页 |
| 文件大小： | 336K |
| 代理商： | 72825LB15PFI9 |
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Figure 25. Write Cycle Timing with Double Register-Buffered
FF (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then the
FF deassertion time may be delayed an extra WCLK cycle.
2.
LD = HIGH.
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then the
FF deassertion may be delayed an extra WCLK cycle.
2.
LD = HIGH.
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
D0 - D17
WEN
RCLK
FF
REN
tENH
Q0 - Q17
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
tSKEW1
DATA WRITE
3139 drw 24
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tA
tENS
tSKEW1
tDS
tA
Wd
(1)
WCLK
D0 - D17
WEN
FF
RCLK
REN
tDS
tWFF
DATA IN VALID
NO OPERATION
(1)
tSKEW1
3139 drw 25
tENS
tDH
tENH
1
2
tCLKH
tCLKL
tCLK
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