参数资料
型号: 73S1209F-68IMR/F
厂商: Maxim Integrated Products
文件页数: 105/123页
文件大小: 0K
描述: IC SMART CARD READER 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: 73S12xx
核心处理器: 80515
芯体尺寸: 8-位
速度: 24MHz
连通性: I²C,智能卡,UART/USART
外围设备: LED,POR,WDT
输入/输出数: 9
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-VFQFN 裸露焊盘
包装: 带卷 (TR)
73S1209F Data Sheet
DS_1209F_004
Smart Card VCC Control/Status Register (VccCtl): 0xFE03
0x00
This register is used to control the power up and power down of the integrated smart card interface. It is
used to determine whether to apply 5V, 3V, or 1.8V to the smart card. Perform the voltage selection with
one write operation, setting both VCCSEL.1 and VCCSEL.0 bits simultaneously. The VDDFLT bit (if
enabled) will provide an emergency deactivation of the internal smart card slot. See the VDD Fault
Detect Function section for more detail.
Table 76: The VccCtl Register
MSB
LSB
VCCSEL.1 VCCSEL.0
VDDFLT
RDYST
VCCOK
SCPWRDN
Bit
Symbol
Function
VccCtl.7
VCCSEL.1
Setting non-zero value for bits 7,6 will begin activation sequence with target
Vcc as given below:
State
VCCSEL.1
VCCSEL.0
VCC
1
0
0V
2
0
1
1.8V
3
1
0
3.0V
4
1
5V
A card event or VCCOK going low will initiate a deactivation sequence.
When the deactivation sequence for RST, CLK and I/O is complete, VCC will
be turned off. When this type of deactivation occurs, the bits must be reset
before initiating another activation.
VccCtl.6
VCCSEL.0
VccCtl.5
VDDFLT
If this bit is set = 0, the CMDVCC3B and CMDVCC5B outputs are
immediately set = 1 to signal to the companion circuit to begin deactivation
when there is a VDD Fault event. If this bit is set = 1 and there is a VDD
Fault, the firmware should perform a deactivation sequence and then set
CMDVCC3B or CMDVCC5B = 1 to signal the companion circuit to set
VCC = 0.
VccCtl.4
RDYST
If this bit is set = 1, the activation sequence will start when bit VCCOK is
set = 1. If not set, the deactivation sequence shall start when the VCCTMR
times out.
VccCtl.3
VCCOK
(Read only). Indicates that VCC output voltage is stable.
VccCtl.2
VccCtl.1
VccCtl.0
SCPWRDN
This bit controls the power-down mode of the 73S1209F circuit.
1 = power down, 0 = normal operation.
82
Rev. 1.2
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