参数资料
型号: 73S8009R-DB
厂商: Maxim Integrated Products
文件页数: 12/18页
文件大小: 0K
描述: BOARD DEMO 73S8009R 28-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *

73S8009R Demo Board User Manual
UM_8009R_065
5 73S8009R Demo Board Schematics, PCB Layouts and Bill of Materials
5.1
Schematics
5.0V
SCLK
SIO
SC4
SC8
OFF
GND
GND
GND
+5V
+5V
J1
1
2
3
4
5
6
7
8
9
10
J7
BNC
1
CLKIN
SELECT
JP1
1 SCLK
2
3 EXTCLK
VPC
SELECT
TP1
5V
C1
C2
10uF PGND
0.1uF
SSM_110_L_SV
J2
R2
3.3V
1
2
3
4
5
6
SCLK
SIO
S_C4
S_C8
INT2
49.9
C1, C2 and C8 must be placed
within 5mm of the U1 pins and
VDD
SELECT
TP9
7
connected by thick track (wider
8
9
10
5.0V
5V
C3
10uF
U1
than 0.5mm)
VDD
3.3V
TSM_110_01_L_SV
R4
0
+3.3V
J3
RDY 1
CS 2
RESET 3
TEST 4
PWRDN 5
CMDVCC5 6
CMDVCC3 7
RSTIN 8
GND 9
10
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CS
RESET
N/C
0FF
I/OUC
AUX1UC
AUX2UC
CMDVCC5
CMDVCC3
RSTIN
CLKIN
RDY
PWRDN
TEST
VDD
GND
PRES
I/O
AUX1
AUX2
VCC
RST
GND
CLK
N/C
N/C
PRES
VPC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C8
0.1uF
J4
1
2
3
4
5
6
7
8
9
10
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
GND
3.3V
C10
TP2
1
2
R1
PWRDN
PULL-DOWN
SELECT
73S8009R
R7
0
R8
Ru
R9
Ru
These resistors are
not populated
TSM_110_01_L_SV
10uF
20K
R10
Ru
C11
3.3uF
R11
Rd
R12
Rd
TP3
J1 and J3 are placed on the bottom.
are placed on the top side.
J2 and J4
TP4
1
2
VCC
J1 and J3 must be aligned with J8 and J9 on the
1121 evaluation board (E1121T8) respectivly in
order for this board to be stacked on it.
R13
Rd
I/O
TP6
1
2
TP5
1
2
RST
TP3 to TP8 to be placed
J1 must be aligned with J2 and J3 must be
aligned with J4 in order for this daughter
board to be stacked on another.
JP5
1
2
3
PRES
PRES
C8
1
2
TP7
1
2
TP8
CLK
very close to the pads
of J5
CARD DETECT
POLARITY SELECT
JP6
GND
1
2
C4
1
2
3
VDD
C12
27pF
C13
27pF
VDD
J5
Smart Card Connector
J6
SIM/SAM Connector
Figure 4: 73S8009R Electrical Schematic
12
Rev. 1.2
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