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| 型号： | 73S8014RT-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 73S8010RT 20-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
73S8014R/RN/RT 20SO Demo Board User Manual
UM_8014_010
3
3.1
Use of the Board: Hardware
Board Description: Jumpers, Switches and Test Points
The items described in the following tables refer to the flags in Figure 2.1
Table 1: Demo Board Description
Item #
(Figure
2.1)
1
Schemati
c & PCB
Silk-print
Reference
J2
Name
Board 5V
supply and
host digital
interface
Use
Connector that gathers the 5V supply of the board, the
73S8014R/RN/RT data interface (IOUC), external clock (SCLK)
and interrupt ( OFF ) pins. Note that the external clock (SCLK) can
be left open when JP1 is in position XTAL.
Also note that the 5V power supply pin can be left open when JP2
is in position 3.3V (= support of 3V cards only).
2
JP3
VDD Select
Jumper to select the digital voltage, between 5V or 3.3V This
setting defines the interfacing voltage with the host microcontroller.
It also provides internal supply voltage for internal circuitry to the
73S8014R/RN/RT.
The default setting is in the 3.3V position.
3
4
5
9
6
TP7
TP5
TP3
TP4
J4
Test Points:
CLK
RST
VCC
I/O
Board 3.3V
supply and
digital control
signals
2-pin test points for each respective smart card signal. The pin
label name is the respective signal (i.e. VCC, CLK) and the other
pin is GND.
Connector that gathers the 3.3V supply of the board, the
73S8014R/RN/RT host control signal pins RSTIN, CMDVCC /
CMDVCC% , 5V/ #V / CMDVCC# , CLKDIV2 and CLKDIV1.
Note that the 3.3V power supply pin can be left open when JP3 is
in position 5V.
7
TP1
PIN12
(VDDF_ADJ)
VDD voltage fault adjustment. Pin to the left is connected to the
VDDF_ADJ pin of the 73S8014R/RN/RT and the pin to the right is
GND. When either a resistor R3, or a resistor network R1 and R3
is populated on the board, it adjusts the VDD fault level that
internally triggers a card deactivation sequence.
By default, the resistors R1 and R3 are not connected. It provides
a VDD fault level of 2.3V typical (internally set to the
73S8014R/RN/RT).
Refers to the 73S8014R/RN/RT Data Sheet for further information
about VDD fault level and determination of these resistor values.
8
J6
Smart Card
Connector
SIM/SAM smart card format connector.
Note that J6 is wired is parallel to the smart card connector J5
(underneath the PCB). No SIM/SAM should be inserted when
using the credit-card size connector J5.
10
JP1
Clock
selection.
Jumper to select between a crystal and external clock as the
frequency reference to the device. The default setting is for a
crystal.
11
J5
Smart Card
Connector
Smart card connector.
When inserting a card (credit card size format), contacts must face
up.
10
Rev. 1.0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 73S8014RT-IL/F | 功能描述:输入/输出控制器接口集成电路 Smart Card Interface Comp w/8024 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| 73S8014RT-IL/F1 | 功能描述:输入/输出控制器接口集成电路 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| 73S8014RT-IL/F2 | 功能描述:输入/输出控制器接口集成电路 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| 73S8014RT-IL/F3 | 功能描述:输入/输出控制器接口集成电路 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| 73S8014RT-ILR/F | 功能描述:输入/输出控制器接口集成电路 Smart Card Interface Comp w/8024 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
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