参数资料
型号: 73S8023C-DB
厂商: Maxim Integrated Products
文件页数: 5/27页
文件大小: 0K
描述: BOARD DEMO 73S8023C 32-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
DS_8023C_019
73S8023C Data Sheet
Rev. 1.5
13
Figure 5: Asynchronous Activation Sequence – RSTIN Low When
CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the
CMDVCC low while the RSTIN is high:
1.
CMDVCC is set low.
2.
Next, the internal VCC control circuit checks the presence of VCC at t1. In normal operation, the
voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC
3.
Due to the fall of RSTIN at t
to the card is turned off.
2
4.
CLK is applied to the card at the end of t
, turn I/O (AUX1, AUX2) to reception mode.
3
5.
RST is to be a copy of RSTIN after t
after I/O is in reception mode.
4. RSTIN may be set high before t 4, however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
t1
t2
t3
t4
RST
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5s, I/O goes to reception state
t3 = > 0.5s, CLK active
t4
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CMDVCC
VCC
IO
CLK
RSTIN
t1
t2
t3
t4
RST
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 s, I/O goes to reception state
t3
≥ 0.5 s, CLK starts
t4
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
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