参数资料
型号: 74LVC1G74GD,125
厂商: NXP Semiconductors
文件页数: 1/25页
文件大小: 0K
描述: IC FLIP-FLOP D POS-EDGE 8-XSON
产品培训模块: Logic Packages
特色产品: MicroPak?
标准包装: 3,000
系列: 74LVC
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 1
每个元件的位元数: 1
频率 - 时钟: 200MHz
延迟时间 - 传输: 2.5ns
触发器类型: 正边沿
输出电流高,低: 32mA,32mA
电源电压: 1.65 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-XFDFN
包装: 带卷 (TR)
其它名称: 568-9313-2
74LVC1G74GD,125-ND
74LVC1G74GD-G
74LVC1G74GD-G-ND
935286752125
1.
General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (V
CC =3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 Cto+85 C and 40 Cto+125 C
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 12 — 2 April 2013
Product data sheet
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