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参数资料
| 型号： | 750108 |
| 厂商： | Wurth Electronics Inc |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR LT3748 |
| 设计资源： | LT3748 Design Schematic/Tips |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，隔离 |
| 功率 - 输出： | 30W |
| 输出电压： | 12V |
| 电流 - 输出： | 2.5A |
| 输入电压： | 22 ~ 75 V |
| 稳压器拓扑结构： | 回扫 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LT3748 |
| 相关产品： | LT3748HMS#TRPBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP LT3748HMS#PBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP LT3748IMS#TRPBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP LT3748IMS#PBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP LT3748EMS#TRPBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP LT3748EMS#PBF-ND - IC REG CTRLR FLYBK ISO CM 16MSOP |
| 其它名称： | 732-3308 |
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LT3748
APPLICATIONS INFORMATION
( V OUT + V F(DIODE) ) ? R SENSE ? t SETTLE(MIN) ? N PS
Minimum Primary Inductance Requirements
The LT3748 obtains output voltage information from the
external MOSFET drain voltage when the secondary winding
conducts current. The sampling circuitry needs a minimum
of 400ns to settle and sample the output voltage while the
MOSFET switch is off. This required settle and sample
time is controlled by external components independent of
the minimum off-time of the GATE pin as specified in the
Electrical Characteristics table. The electrical specification
minimum off-time is based on an internal timer and acts
as a maximum frequency clamp. The following equation
gives the minimum value for primary-side magnetizing
inductance:
L PRI ≥
V SENSE(MIN)
V SENSE(MIN) = 15mV
t SETTLE(MIN) = 400ns
N PS = Ratio of primary windings to secondary windings
In addition to the primary inductance requirement for
minimum settling and sampling time, the LT3748 has
internal circuit constraints that prevent it from setting the
GATE node high for shorter than approximately 250ns.
If the inductor current exceeds the desired current limit
during that time oscillation may occur at the output as
the current control loop will lose its ability to regulate.
Therefore, the following equation relating to maximum
input voltage must also be followed in selecting primary-
side magnetizing inductance:
Output Power
Because the MOSFET power switch is located outside the
LT3748, the maximum output power is primarily limited
by external components. Output power limitations can
be separated into three categories—voltage limitations,
current limitations and thermal limitations.
The voltage limitations in a flyback design are primarily
the MOSFET switch V DS(MAX) and the output diode re-
verse-bias rating. Increasing the voltage rating of either
component will typically decrease application efficiency if
all else is equal and the voltage requirements on each of
those components will be directly related to the windings
ratio of the transformer, the input and output voltages
and the use of any additional snubbing components.
The MOSFET V DS(MAX) must theoretically be higher than
V IN(MAX) + (V OUT ? N PS ) and the output diode reverse bias
must be higher than V OUT + (V IN(MAX) /N PS ), though leak-
age inductance spikes on both the drain of the MOSFET
and the anode of the output diode may more than double
that requirement (see section on leakage inductance for
more details on snubbers). Figure 1 illustrates the effect
on available output power for several MOSFET voltage
ratings while continuously maximizing windings ratio
for input voltage with a fixed MOSFET current limit and
output voltage. Increasing the MOSFET rating increases
the possible windings ratio and or maximum input voltage
and can increase the available output power for a given
application. Both figures assume no leakage inductance
and high efficiency.
L PRI ≥
V IN(MAX) ? R SENSE ? t ON(MIN)
V SENSE(MIN)
50
40
V DS = 200V
V DS = 150V
t ON(MIN) = 250ns
The last constraint on minimum inductance value would
relate to minimum full-load operating frequency, f MIN , and
is derived from f SW = 1/(t ON + t OFF ):
L PRI ≤ V IN(MIN) ? (V OUT + V F(DIODE) ) ? N PS /(f SW(MIN) ? I LIM ?
30
20
10
V DS = 100V
((V OUT + V F(DIODE) ) ? N PS + V IN(MIN) ))
0
0
20
40
60
80
100
The minimum operating frequency may be lower than
the calculated number due to delays in detecting current
INPUT VOLTAGE (V)
3748 F01
limit and detecting boundary mode that are specific to
each application.
Figure 1. Maximum Output Power at 12V OUT with a
3A I LIM and Maximum V DS = 100V, 150V, 200V
3748fa
11
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