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参数资料
| 型号： | 78P2351-IGTR/F |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 39/42页 |
| 文件大小： | 0K |
| 描述： | LINE INTERFACE UNIT 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | E4，OC-3，STM1-E |
| 电源电压： | 3.15 V ~ 3.45 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（16x16） |
| 包装： | 带卷 (TR) |
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78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 6 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
provided to the 78P2351.
In this mode, the
78P2351 will recover a transmit clock from the serial
plesiochronous data and bypass the internal FIFO
and re-timing block. This mode is commonly used
for mezzanine cards, modules, and any application
where the reference clock can’t always be
synchronous to the transmit source clock/data.
TDK
78P2351
Framer/
Mapper
NRZ
140 / 155 MHz
Reference
Clock
SODP/N
SOCKP/N
SIDP/N
CKREFP
RXP/N
CMIP/N
XFMR
CMI
Coax
XO
Figure 3: Plesiochronous data only
(Tx CDR enabled, FIFO bypassed)
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4
÷ 4) or
38.88MHz (STM1
÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data must be source synchronous to the
provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2351 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be re-
timed using the recovered receive clock.
HW Control Pins
SW Control Bits
Parallel
Mode
SDI_PAR
CKMODE
PAR
PMODE
Slave
High
Low
1
0
Slave +
*Loop-timing
High
Float
1
0
Master
High
1
*To enable loop-timing in software mode, set
SMOD[1:0]=11
4-bit CMOS TTL
TDK
78P2351
Framer/
Mapper
Reference
Clock
CKREFP/N
RXP/N
CMIP/N
XFMR
CMI
Coax
PO[3:0]D
POCK
PIxCK
PI[3:0]D
34/39 MHz
Figure 4: Slave Parallel Mode
4-bit CMOS TTL
TDK
78P2351
Framer/
Mapper
Reference
Clock
CKREFP/N
RXP/N
CMIP/N
XFMR
CMI
Coax
PO[3:0]D
POCK
PTOCK
PI[3:0]D
34/39 MHz
Figure 5: Master Parallel Mode
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERR register signal will be asserted.
This
signal can be used to trigger an interrupt.
This
interrupt event is automatically cleared when a FIFO
Reset (FRST) pulse is applied, and the FIFO is re-
centered.
Notes:
1) External remote loopbacks (i.e. loopback
within
framer)
are
not
possible
in
synchronous
operation
(FIFO
enabled)
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2351 is configured for loop-timing
operation.
2) During IC power-up or transmit power-up,
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow. As such, the FIFO should be
manually reset using FRST anytime the
transmitter is powered-up.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 78P2351R | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-DB | 功能描述:界面开发工具 78P2351R Demo Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| 78P2351R-IM | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-IM/F | 功能描述:接口 - 专用 Serial 155M NRZ to CMI Converter RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| 78P2351R-IMR | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
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