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参数资料
| 型号： | 8400110EKILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, QCC32 |
| 封装： | 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 |
| 文件页数： | 11/14页 |
| 文件大小： | 699K |
| 代理商： | 8400110EKILF |
ICS8400110I Data Sheet
LOW JITTER, TELCOM RATE-CONVERSION PLL
ICS8400110EKI REVISION A NOVEMBER 9, 2009
6
2009 Integrated Device Technology, Inc.
Parameter Measurement Information
Output Load AC Test Circuit
RMS Phase Jitter
Output Pulse Width
Cycle-to-Cycle Jitter
Period Jitter Peak-to-Peak
Output Rise/Fall Time
SCOPE
Qx
LVCMOS
GND
VDD
VDDA
1.65V±0.15V
-1.65V±0.15V
1.65V±0.15V
VDDA
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under Offset Frequency Markers
Noise
P
o
w
er
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
C250,
C650
C250,
C650
tcycle n
tcycle n+1
tjit(cc) =
|tcycle n – tcycle n+1|
1000 Cycles
VOH
VREF
VOL
Mean Period
(First edge after trigger)
10,000 cycles
Reference Point
(Trigger Edge)
Histogram
tjit (pk-pk)
20%
80%
20%
tR
t F
C250,
C650
NOTE: Using 30pF
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