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参数资料
| 型号： | 8400110EKILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, QCC32 |
| 封装： | 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 |
| 文件页数： | 8/14页 |
| 文件大小： | 699K |
| 代理商： | 8400110EKILF |
ICS8400110I Data Sheet
LOW JITTER, TELCOM RATE-CONVERSION PLL
ICS8400110EKI REVISION A NOVEMBER 9, 2009
3
2009 Integrated Device Technology, Inc.
Functional Description
The PLL of ICS8400110I consists of a phase detector, a loop filter
and a Voltage Controlled Oscillator (VCO). In the normal mode of
operation, the VCO provides an output clock signal that is frequency
and phase locked to the input reference clock (REF). In free-run
mode, VCO is locked to 25MHz input with an accuracy equal to the
accuracy of the OSCi 25MHz clock.
Lock Indicator
The Lock detector monitors if the output clock phase is within 90° of
the input reference (REF). If the difference between input reference
clock (REF) and output is more than 90°, LOCK output is LOW. The
monitor than looks for eight consecutive clocks within 22.5° of the
reference, before setting the LOCK to a HIGH.
REF_FAIL
The REF_FAIL signal is HIGH when reference clock (REF) shows
greater than 130ppm variation in frequency, there are more than
three consecutive edges missing, or there is an abrupt phase shift in
the reference clock REF. Under any of these circumstances the PLL
input will be switched from primary reference clock (REF) to crystal.
When the primary reference clock (REF) is restored and REF_FAIL
sets to LOW, the PLL input is switched back to the primary reference
clock (REF).
Modes of Operation
The ICS8400110I device has two modes of operation; normal mode
and free-run mode. The device powers up in free-run mode, it
automatically transitions to normal mode if a valid reference clock
(REF) is available and transitions to free-run mode if the reference
fails. RESET signal also will puts the device in free-run mode.
Freerun Mode
The freerun mode is typically used when an asynchronous clock
source is required or it is used immediately following system
power-up before synchronization is achieved. In free-run mode,
ICS8400110I provides an output clock based on oscillator frequency.
The output is not synchronized to the reference input clock (REF). In
the free-run mode the accuracy of output frequency is equal to the
accuracy of the frequency of the oscillator.
Normal Mode
The normal mode is typically used when a synchronous clock is
required. In normal mode, ICS8400110I provides an output clock
which is synchronized to the input (REF).
Lock Time
This is the time it takes the PLL to lock to the input reference clock
REF. Lock occurs when the input signal and output signal are aligned
in phase and frequency with respect to each other. LOCK time is
affected by many factors which include:
- Initial input to output phase difference
- Initial input to output frequency difference
- PLL loop bandwidth
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