参数资料
型号: 89HPES12NT3ZABC
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线控制器
英文描述: 12-lane 3-Port Non-Transparent PCI Express㈢ Switch
中文描述: PCI BUS CONTROLLER, PBGA324
封装: 19 X 19 MM, 1 MM PITCH, BGA-324
文件页数: 4/29页
文件大小: 263K
代理商: 89HPES12NT3ZABC
4 of 29
April 11, 2007
IDT 89HPES12NT3 Data Sheet
Pin Desc ription
The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
S ignal
Type
Name/Desc ription
PEALREV
I
PCI Express Port A Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[3:0]
PEARN[3:0]
I
PCI Express Port A Serial Data Receive.
Differential PCI Express receive
pairs for port A.
PEATP[3:0]
PEATN[3:0]
O
PCI Express Port A Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port A
PEBLREV
I
PCI Express Port B Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PEBRP[3:0]
PEBRN[3:0]
I
PCI Express Port B Serial Data Receive.
Differential PCI Express receive
pairs for port B.
PEBTP[3:0]
PEBTN[3:0]
O
PCI Express Port B Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port B
PECLREV
I
PCI Express Port C Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[3:0]
PECRN[3:0]
I
PCI Express Port C Serial Data Receive.
Differential PCI Express receive
pairs for port C.
PECTP[3:0]
PECTN[3:0]
O
PCI Express Port C Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the systemlogic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determned by the REFCLKMsignal.
REFCLKM
I
PCI Express Reference Clock Mode Select.
These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
S ignal
Type
Name/Desc ription
MSMBADDR[4:1]
I
Master SMBus Address.
These pins determne the SMBus address of the
serial EEPROMfromwhich configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROMor I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins (Part 1 of 2)
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相关代理商/技术参数
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89HPES12NT3ZABCG 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch
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