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| 型号： | 89HPES12NT3ZABC |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线控制器 |
| 英文描述： | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 中文描述： | PCI BUS CONTROLLER, PBGA324 |
| 封装： | 19 X 19 MM, 1 MM PITCH, BGA-324 |
| 文件页数： | 6/29页 |
| 文件大小： | 263K |
| 代理商： | 89HPES12NT3ZABC |
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April 11, 2007
IDT 89HPES12NT3 Data Sheet
S ignal
Type
Name/Desc ription
CCLKDS
I
Common Clock Downstream.
When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstreamdevice
and the downstreamport.
CCLKUS
I
Common Clock Upstream.
When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstreamdevice and
the upstreamport.
MSMBSMODE
I
Master SMBus Slow Mode.
The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PENTBRSTN
I
Non-Transparent Bridge Reset.
Assertion of this signal indicates a reset
on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.
PERSTN
I
Fundamental Reset.
Assertion of this signal resets all logic inside the
PES12NT3 and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt.
When this signal is asserted during a PCI Express fundamental
reset, the PES12NT3 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode.
These configuration pins determne the PES12NT3 switch
operating mode.
0x0 - Reserved
0x1 - Reserved
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved
Table 4 System Pins
S ignal
Type
Name/Desc ription
JTAG_TCK
I
JTAG Clock
. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the systemclock with a nomnal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input
. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
相关PDF资料 |
PDF描述 |
|---|---|
| 89HPES12NT3ZABCG | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12T3G2 | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABC | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABCG | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES16NT2 | 16-Lane 2-Port Non-Transparent PCI Express㈢ Switch |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12NT3ZABCG | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
| 89HPES12NT3ZBBC8 | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:带卷（TR） 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:750 |
| 89HPES12NT3ZBBCG | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
| 89HPES12NT3ZBBCG8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
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