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参数资料
| 型号： | 9250CF-10LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, GREEN, SSOP-56 |
| 文件页数： | 7/18页 |
| 文件大小： | 452K |
| 代理商： | 9250CF-10LFT |
15
ICS9250- 10
General Layout Precautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of diagram.
2) 47 ohm / 56pf RC termination should be
used on all over 50MHz outputs.
3) Optional crystal load capacitors are
recommended.
ConnectionstoVDD:
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01F ceramic
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