参数资料
型号: 932S421CFLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: ROHS COMPLIANT, MO-118, SSOP-56
文件页数: 7/23页
文件大小: 242K
代理商: 932S421CFLFT
15
Integrated
Circuit
Systems, Inc.
ICS932S421C
1460E—08/25/09
SMBus Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
0
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
1
SMBus Table: Device ID Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
DID7
R
-
0
Bit 6
DID6
R
-
0
Bit 5
DID5
R
-
1
Bit 4
DID4
R
-
0
Bit 3
DID3
R
-
1
Bit 2
DID2
R
-
0
Bit 1
DID1
R
-
1
Bit 0
DID0
R
-
1
SMBus Table: M/N Programming & Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
M/N_EN
CPU and SRC
M/N Programming
Enable
RW
Disable
Enable
0
Bit 6
CPU_STOP Control
Stop non-free running PC
and SRC clocks.
RW
Stop
Run
1
Bit 5
0
Bit 4
0
Bit 3
SRC Alternate Frequency (96% of
Nominal)
Set SRC = 96 MHz and
PCI = 32 MHz
Only active if
Byte 10, bit 2 = 1
RW
Normal
Alternate
Frequency
0
Bit 2
CPU Alternate Frequency (96% of
Nominal) Only active if latched
frequency is 166 MHz or 333
MHz.
Set alternate CPU
frequency:
166 MHz to 160 MHz
333 MHz to 320 MHz
RW
Normal
Alternate
Frequency
0
Bit 1
REF1 Drive Strength
1X or 2X
RW
1
Bit 0
REF0 Drive Strength
1X or 2X
RW
1
RESERVED
-
See REF Drive Strength
Functionality Table
55
SRC, PCI
-
CPU
-
CPU
54
Byte 8
Byte 9
Byte 10
-
Device ID
(2B hex)
Byte Count Programming
b(7:0)
Writing to this register will
configure how many bytes will
be read back, default is 8
bytes.
(0 to 7)
RESERVED
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