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| 型号： | 935262730528 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件页数： | 11/52页 |
| 文件大小： | 303K |
| 代理商： | 935262730528 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
19
Table 5.
MR2 - Mode Register 2
The MR2 register provides basic channel setup control that may need more frequent updating.
Bits 7:6
Bit 5
Bit 4
Bit 3:2
Bit 1:0
Channel Mode
TxRTS Control
CTSN Enable Tx
RxINT
Stop Length
00 = normal
01 = Auto echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
00 = RRDY
01 = Half Full
10 = 3/4 Full
11 = Full
00 = 1.0
01 = 1.5
10 = 2.0
11 = 9/16
MR2[7:6] - Mode Select
The Quad UART can operate in one of four modes: MR2[7:6] = b’00
is the normal mode, with the transmitter and receiver operating
independently.
MR2[7:6] = b’01 places the channel in the automatic echo mode,
which automatically re transmits the received data. The following
conditions are true while in automatic echo mode:
Received data is re-clocked and re-transmitted on the TxD
output.
The receive clock is used for the transmitter.
The receiver must be enabled, but the transmitter need not be
enabled.
The TxRDY and TxEMT status bits are inactive.
The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received.
Character framing is checked, but the stop bits are retransmitted
as received.
A received break is echoed as received until the next valid start
bit is detected.
CPU to receiver communication continues normally, but the CPU to
transmitter link is disabled.
Two diagnostic modes can also be selected.
MR2[7:6] = b’10 selects local loop back mode. In this mode:
The transmitter output is internally connected to the receiver
input.
The transmit clock is used for the receiver.
The TxD output is held high.
The RxD input is ignored.
The transmitter must be enabled, but the receiver need not be
enabled.
CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loop back mode,
selected by MR2[7:6] = b’11. In this mode:
Received data is re-clocked and re-transmitted on the TxD
output.
The receive clock is used for the transmitter.
Received data is not sent to the local CPU, and the error status
conditions are inactive.
The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
The receiver must be enabled, but the transmitter need not be
enabled.
Character framing is not checked, and the stop bits are
retransmitted as received.
A received break is echoed as received until the next valid start
bit is detected.
MR2[5] - Transmitter Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2[5] = 1
causes RTSN to be reset automatically one bit time after the
characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission of a message as follows:
Program auto reset mode: MR2[5]= 1.
Enable transmitter.
Assert RTSN via command.
Send message.
After the last character of the message is loaded to the TxFIFO,
disable the transmitter. Before disabling the transmitter be sure
the Status Register TxEMT bit is NOT set (i.e., the transmitter is
not underrun). The underrun condition is indicated by the TxEMT
bit in the SR being set. The codition occurs immediately upon
enabling the transmitter and persists until a character is loaded
to the TxFIFO. The Underrun condition will not be a problem as
long as the controlling processor keeps up with the transmitter
data flow. The proper operation of this feature assumes that the
transmitter is busy (not underrun) when the disable is issued.
The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
NOTE: When the transmitter controls the RTSN pin, the meaning of
the pin is COMPLETELY changed. It has nothing to do with the
normal RTSN/CTSN “handshaking”. It is usually used to mean “end
of message” and to “turn the line around” in simplex
communications.
MR2[4] - Clear to Send Control
The state of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the state of CTSN
each time it is ready to begin sending a character. If it is asserted
(low), the character is transmitted. If it is negated (high), the TxD
output remains in the marking state and the transmission is delayed
until CTSN goes low. Changes in CTSN, while a character is being
transmitted, do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:2] - RxINT control field
Controls when interrupt arbitration for a receiver begins based on
RxFIFO fill level. This field allows interrupt arbitration to begin when
the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1
character.
MR2[1:0] - Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can
be programmed for character lengths of 6, 7, and 8 bits. For a
character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.
In all cases, the receiver only checks for a mark condition at the
center of the first stop bit position (one bit time after the last data bit,
or after the parity bit if parity is enabled). If an external 1X clock is
used for the transmitter, MR2[1] = 0 selects one stop bit and
MR2[1] = 1 selects two stop bits to be transmitted.
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