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| 型号： | 935262730528 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件页数： | 13/52页 |
| 文件大小： | 303K |
| 代理商： | 935262730528 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
20
Table 6.
RxCSR and TxCSR - Receiver and Transmitter Clock Select Registers
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b’000. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown below
will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
Bits 7:5
Bits 4:0
Reserved
Transmitter/Receiver Clock select code, (see Clock Mux Table below)
Table 7.
Data Clock Mux
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Clock Select Code
Bits 4:0
Clock selection,
CCLK = 3.6864 MHz
Clock Select Code
Clock selection,
CCLK = 3.6864 MHz
00000
BRG - 50
10000
BRG - 19.2K
00001
BRG - 75
10001
BRG - 28.8K
00010
BRG - 150
10010
BRG - 38.4K
00011
BRG - 200
10011
BRG - 57.6K
00100
BRG - 300
10100
BRG - 115.2K
00101
BRG - 450
10101
BRG - 230.4K
00110
BRG - 600
10110
Gin0
00111
BRG - 900
10111
Gin1
01000
BRG - 1200
11000
BRG C/T 0
01001
BRG - 1800
11001
BRG C/T 1
01010
BRG - 2400
11010
Reserved
01011
BRG - 3600
11011
I/O2 rcvr, I/O3 xmit -16x
01100
BRG - 4800
11100
I/O2 rcvr, I/O3 xmit-1x
01101
BRG - 7200
11101
Reserved
01110
BRG - 9600
11110
Reserved
01111
BRG - 14.4K
11111
Reserved
Table 8.
CR - Command Register
CR is used to write commands to the Quad UART.
Bits 7:3
Bit 2
Bit 1
Bit 0
Channel Command codes see
“Command Register Table”
1 = Hold present condition of Tx & Rx Enables
0 = Change Tx & Rx enable conditions
1 = Enable Tx
0 = Disable Tx
1 = Enable Rx
0 = Disable Rx
CR[2] - Lock TxD and RxFIFO enables
If set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register. WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition
of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[1] - Enable Transmitter
A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] - Enable Receiver
A one written to this bit enables operation of the receiver. If not in
the special Wake-up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately - a character being
received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake-up
mode is programmed, the receiver operates even if it is disabled
(see Wake-up Mode).
CR[7:3] - Miscellaneous Commands (See Table below)
The encoded value of this field can be used to specify a single
command as follows:
00000
No command.
00001
Reserved.
00010
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
00011
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
00100
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
00101
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.
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