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参数资料
| 型号： | 935263686518 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 6 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64 |
| 文件页数： | 4/22页 |
| 文件大小： | 170K |
| 代理商： | 935263686518 |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
12
17.3
Bushold and Link/PHY single capacitor
galvanic isolation
17.3.1
Bushold
The PDI1394P11A uses an internal bushold circuit on each of the
indicated pins to keep these CMOS inputs from “floating” while being
driven by a 3-Stated device or input coupling capacitor.
Unterminated high impedance inputs react to ambient electrical
noise which cause internal oscillation and excess power supply
current draw.
The following pins have bushold circuitry enabled when the ISO– pin
is in the logic “1” state:
Pin No.
Name
Function
2
LPS
Link power status line
3
LREQ
Link request line
7
PD
Power down pin
11
CTL0
Phy/Link Interface bi-directional control line 0
12
CTL1
Phy/Link Interface bi-directional control line 1
13
D0
Phy/Link Interface bi-directional data line 0
14
D1
Phy/Link Interface bi-directional data line 1
15
D2
Phy/Link Interface bi-directional data line 2
16
D3
Phy/Link Interface bi-directional data line 3
Philips bushold circuitry is designed to provide a high resistance
pull-up or pull-down on the input pin. This high resistance is easily
overcome by the driving device when its state is switched. Figure 6
shows a typical bushold circuit applied to a CMOS input stage. Two
weak MOS transistors are connected to the input. An inverter is also
connected to the input pin and supplies gate drive to both
transistors. When the input is LOW, the inverter output drives the
lower MOS transistor and turns it on. This re-enforces the LOW on
the input pin. If the logic device which normally drives the input pin
were to be 3-Stated, the input pin would remain “pulled-down” by the
weak MOS transistor. If the driving logic device drives the input pin
HIGH, the inverter will turn the upper MOS transistor on,
re-enforcing the HIGH on the input pin. If the driving logic device is
then 3-Stated, the upper MOS transistor will weakly hold the input
pin HIGH.
The PHY’s outputs can be 3-Stated and single capacitor isolation
can be used with the Link; both situations will allow the Link inputs to
float. With bushold circuitry enabled, these pins are provided with dc
paths to ground, and power by means of the bushold transistors;
this arrangement keeps the inputs in known logical states.
SV00911
INPUT PIN
INTERNAL
CIRCUITS
Figure 6.
Bushold circuit
17.3.2
Single capacitor isolation
The circuit example (Figure 7) shows the connections required to
implement basic single capacitor Link/PHY isolation.
The RESET, C/LKON, PD, and LPS pins need special consideration
to implement an isolation scheme. Details can be found in the
Philips Isolation Application Note AN2452.
NOTE: The isolation enablement pins on both devices are in their
“1” states, activating the bushold circuits on each part. The bushold
circuits provide local dc ground references to each side of the
isolating/coupling capacitors. Also note that ground
isolation/signal-coupling must be provided in the form of a parallel
combination of resistance and capacitance as indicated in
IEEE 1394–1995.
D0
D1
D2
D3
PHYCTL0
PHYCTL1
LREQ
SYSCLK
ISO–
Cc
PHY
PDI1394P11A
ISOLATED PHY GROUND
Cc
Cr
Cc
1MEG
Cc
PHY D0
PHY D1
PHY D2
PHY D3
PHYCTL0
PHYCTL1
LREQ
SCLK
ISO_N
LINK
PDI1394Lxx
13
14
15
16
11
12
3
9
62
APPLICATION GROUND
APPLICATION
+3.3V
ISOLATED
+3.3V
SV01048
Cc = 0.001
F; Cr = 0.1F
Figure 7.
Single capacitor Link/PHY isolation
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